TCAN4550Can.hxx

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#ifndef _FREERTOS_DRIVERS_COMMON_TCAN4550CAN_HXX_
#define _FREERTOS_DRIVERS_COMMON_TCAN4550CAN_HXX_
 
#include "Can.hxx"
#include "DummyGPIO.hxx"
#include "SPI.hxx"
 
#include "os/Gpio.hxx"
#include "os/OS.hxx"
#include "utils/Atomic.hxx"
 
#include "can_ioctl.h"
 
#define TCAN4550_DEBUG 0
 
class TCAN4550Can : public Can, public OSThread, private Atomic
{
public:
    TCAN4550Can(const char *name,
                void (*interrupt_enable)(), void (*interrupt_disable)(),
#if TCAN4550_DEBUG
                const Gpio *test_pin = DummyPinWithRead::instance()
#else
                const Gpio *test_pin = nullptr
#endif
               )
        : Can(name, 0, 0)
        , OSThread()
        , interruptEnable_(interrupt_enable)
        , interruptDisable_(interrupt_disable)
        , spiFd_(-1)
        , spi_(nullptr)
        , sem_()
        , mcanInterruptEnable_()
        , txCompleteMask_(0)
        , state_(CAN_STATE_STOPPED)
        , txPending_(false)
        , rxPending_(false)
#if TCAN4550_DEBUG
        , testPin_(test_pin)
#endif
    {
#if TCAN4550_DEBUG
        testPin_->set();
#endif
    }
 
    ~TCAN4550Can()
    {
    }
 
    void init(const char *spi_name, uint32_t freq, uint32_t baud,
              uint16_t rx_timeout_bits);
 
    __attribute__((optimize("-O3")))
    void interrupt_handler()
    {
        int woken = false;
        interruptDisable_();
        sem_.post_from_isr(&woken);
        os_isr_exit_yield_test(woken);
    }
 
    OSMutex *get_spi_bus_lock()
    {
        return &lock_;
    }
 
private:
    static constexpr uint32_t SPI_MAX_SPEED_HZ = 18000000;
 
    static constexpr size_t MRAM_SIZE_WORDS = (2 * 1024) / 4;
 
    // ---- Memory layout ----
    //
    // +-----------------------+
    // | RX FIFO 0, buf 0      | 0x0000
    // | ...                   |
    // | RX FIFO 0, buf 63     | 0x03F0
    // +-----------------------+
    // | TX Event 0 (FIFO)     | 0x0400
    // | ...                   |
    // | TX Event 15 (FIFO)    | 0x047F
    // +-----------------------+
    // | TX Buf 0              | 0x0480
    // | ...                   |
    // | TX Buf 15             | 0x057F
    // +-----------------------+
    // | TX Buf 16 (FIFO)      | 0x0580
    // | ...                   |
    // | TX Buf 31 (FIFO)      | 0x067F
    // +-----------------------+
    // | Unused                | 0x0680
    // +-----------------------+
 
    static constexpr uint32_t RX_FIFO_SIZE = 64;
 
    static constexpr uint32_t TX_EVENT_FIFO_SIZE = 16;
 
    static constexpr uint32_t TX_DEDICATED_BUFFER_COUNT = 16;
 
    static constexpr uint32_t TX_FIFO_SIZE = 16;
 
    static constexpr uint32_t TX_FIFO_BUFFERS_MASK = 0xFFFF0000;
 
    static constexpr uint16_t RX_FIFO_0_MRAM_ADDR = 0x0000;
 
    static constexpr uint16_t TX_EVENT_FIFO_MRAM_ADDR = 0x0400;
 
    static constexpr uint16_t TX_BUFFERS_MRAM_ADDR = 0x0480;
 
    static constexpr uint16_t TX_FIFO_BUFFERS_MRAM_ADDR = 0x0580;
 
    static constexpr uint16_t MRAM_ADDR_OFFSET = 0x8000;
 
    enum Registers : uint16_t
    {
        DEVICE_IDL = 0x0, 
        DEVICE_IDH,       
        REVISION,         
        STATUS,           
 
        MODE = 0x200,        
        TIMESTAMP_PRESCALER, 
        TEST,                
        ECC,                 
 
        INTERRUPT_STATUS = 0x208, 
        MCAN_INTERRUPT_STATUS,    
 
        INTERRUPT_ENABLE = 0x20C, 
 
        CREL = 0x400, 
        ENDN,         
        CUST,         
        DBTP,         
        TEST2,        
        RWD,          
        CCCR,         
        NBTP,         
        TSCC,         
        TSCV,         
        TOCC,         
        TOCV,         
        RSVD1,        
        RSVD2,        
        RSVD3,        
        RSVD4,        
        ECR,          
        PSR,          
        TDCR,         
        RSVD5,        
        IR,           
        IE,           
        ILS,          
        ILE,          
        RSVD6,        
        RSVD7,        
        RSVD8,        
        RSVD9,        
        RSVD10,       
        RSVD11,       
        RSVD12,       
        RSVD13,       
                      //   From here on the register offsets differ between
                      //   implementations:
                      //   TCAN STM32 < register offset
        GFC,          
        SIDFC,        
        XIDFC,        
        RSVD14,       
        XIDAM,        
        HPMS,         
        NDAT1,        
        NDAT2,        
        RXF0C,        
        RXF0S,        
        RXF0A,        
        RXBC,         
        RXF1C,        
        RXF1S,        
        RXF1A,        
        RXESC,        
        TXBC,         
        TXFQS,        
        TXESC,        
        TXBRP,        
        TXBAR,        
        TXBCR,        
        TXBTO,        
        TXBCF,        
        TXBTIE,       
        TXBCIE,       
        RSVD15,       
        RSVD16,       
        TXEFC,        
        TXEFS,        
        TXEFA,        
        RSVD17,       
 
        MRAM = 0x2000, 
    };
 
    // Check alignment
    static_assert(TXEFS * 4 == 0x10F4, "register enum misaligned");
    static_assert(ILE * 4 == 0x105C, "register enum misaligned");
    static_assert(MCAN_INTERRUPT_STATUS * 4 == 0x0824,
                  "register enum misaligned");
 
    enum Command : uint8_t
    {
        WRITE = 0x61, 
        READ  = 0x41, 
    };
 
    struct Mode
    {
        Mode()
            : data(0xC8000468)
        {
        }
 
        union
        {
            uint32_t data; 
            struct
            {
                uint32_t testModeConfig : 1; 
                uint32_t sweDis         : 1; 
                uint32_t reset          : 1; 
                uint32_t wdEnable       : 1; 
                uint32_t reserved1      : 2; 
                uint32_t modeSel        : 2; 
                uint32_t nWkrqConfig    : 1; 
                uint32_t inhDisable     : 1; 
                uint32_t gpio1GpoConfig : 2; 
                uint32_t reserved2      : 1; 
                uint32_t failSafeEnable : 1; 
                uint32_t gpio1Config    : 2; 
                uint32_t wdAction       : 2; 
                uint32_t wdBitSet       : 1; 
                uint32_t nWkrqVoltage   : 1; 
                uint32_t reserved3      : 1; 
                uint32_t testModeEn     : 1; 
                uint32_t gpo2Config     : 2; 
                uint32_t reserved4      : 3; 
                uint32_t clkRef         : 1; 
                uint32_t wdTimer        : 2; 
                uint32_t wakeConfig     : 2; 
            };
        };
    };
 
    struct Dbtp
    {
        Dbtp(uint32_t dsjw, uint32_t dtseg2, uint32_t dtseg1, uint32_t dbrp,
             uint32_t tdc)
            : dsjw(dsjw)
            , dtseg2(dtseg2)
            , dtseg1(dtseg1)
            , dbrp(dbrp)
            , tdc(tdc)
        {
        }
 
        union
        {
            uint32_t data; 
            struct
            {
                uint32_t dsjw      : 4; 
                uint32_t dtseg2    : 4; 
                uint32_t dtseg1    : 5; 
                uint32_t reserved1 : 3; 
                uint32_t dbrp      : 5; 
                uint32_t reserved2 : 2; 
                uint32_t tdc       : 1; 
                uint32_t reserved3 : 8; 
            };
        };
    };
 
    struct Cccr
    {
        Cccr()
            : data(0x00000001)
        {
        }
 
        union
        {
            uint32_t data; 
            struct
            {
                uint32_t init  : 1; 
                uint32_t cce   : 1; 
                uint32_t asm_  : 1; 
                uint32_t csa   : 1; 
                uint32_t csr   : 1; 
                uint32_t mon   : 1; 
                uint32_t dar   : 1; 
                uint32_t test  : 1; 
 
                uint32_t fdoe  : 1; 
                uint32_t brse  : 1; 
                uint32_t rsvd1 : 2; 
                uint32_t pxhd  : 1; 
                uint32_t efbi  : 1; 
                uint32_t txp   : 1; 
                uint32_t niso  : 1; 
 
                uint32_t rsvd2 : 16; 
            };
        };
    };
 
    struct Nbtp
    {
        Nbtp(uint32_t sjw, uint32_t tseg2, uint32_t tseg1, uint32_t brp)
            : ntseg2(tseg2)
            , ntseg1(tseg1)
            , nbrp(brp)
            , nsjw(sjw)
        {
        }
 
        union
        {
            uint32_t data; 
            struct
            {
                uint32_t ntseg2    : 7; 
                uint32_t rsvd1     : 1; 
                uint32_t ntseg1    : 8; 
                uint32_t nbrp      : 9; 
                uint32_t nsjw      : 7; 
            };
        };
    };
 
    struct Tscc
    {
        Tscc()
            : data(0x00000000)
        {
        }
 
        union
        {
            uint32_t data; 
            struct
            {
                uint32_t tss   :  2; 
                uint32_t rsvd1 : 14; 
 
                uint32_t tcp   :  4; 
                uint32_t rsvd2 : 12; 
            };
        };
    };
 
    struct Tscv
    {
        union
        {
            uint32_t data; 
            struct
            {
                uint32_t tsc  : 16; 
                uint32_t rsvd : 16; 
            };
        };
    };
 
    struct Tocc
    {
        Tocc()
            : data(0xFFFF0000)
        {
        }
 
        union
        {
            uint32_t data; 
            struct
            {
                uint32_t etoc  : 1; 
                uint32_t tos   : 2; 
                uint32_t rsvd1 : 5; 
 
                uint32_t rsvd2 : 8; 
 
                uint32_t top : 16; 
            };
        };
    };
 
    struct Tocv
    {
        union
        {
            uint32_t data; 
            struct
            {
                uint32_t toc  : 16; 
                uint32_t rsvd : 16; 
            };
        };
    };
 
    struct Psr
    {
        union
        {
            uint32_t data; 
            struct
            {
                uint32_t lec : 3; 
                uint32_t act : 2; 
                uint32_t ep  : 1; 
                uint32_t ew  : 1; 
                uint32_t bo  : 1; 
 
                uint32_t dlec  : 3; 
                uint32_t resi  : 1; 
                uint32_t rbrs  : 1; 
                uint32_t rfdf  : 1; 
                uint32_t pxe   : 1; 
                uint32_t rsvd1 : 1; 
 
                uint32_t tdcv  : 7; 
                uint32_t rsvd2 : 1; 
 
                uint32_t rsvd3 : 8; 
            };
        };
    };
 
    struct Rxfxc
    {
        Rxfxc()
            : data(0x00000000)
        {
        }
 
        union
        {
            uint32_t data; 
            struct
            {
                uint32_t fsa : 16; 
 
                uint32_t fs   : 7; 
                uint32_t rsvd : 1; 
 
                uint32_t fwm : 7; 
                uint32_t fom : 1; 
            };
        };
    };
 
    struct Rxfxs
    {
        union
        {
            uint32_t data; 
            struct
            {
                uint32_t ffl   : 7; 
                uint32_t rsvd1 : 1; 
 
                uint32_t fgi   : 6; 
                uint32_t rsvd2 : 2; 
 
                uint32_t fpi   : 6; 
                uint32_t rsvd3 : 2;
 
                uint32_t ff    : 1; 
                uint32_t rfl   : 1; 
                uint32_t rsvd4 : 6; 
            };
        };
    };
 
    struct Rxfxa
    {
        Rxfxa()
            : data(0x00000000)
        {
        }
 
        union
        {
            uint32_t data; 
            struct
            {
                uint32_t fai  :  6; 
                uint32_t rsvd : 26; 
            };
        };
    };
 
    struct Txbc
    {
        Txbc()
            : data(0x00000000)
        {
        }
 
        union
        {
            uint32_t data; 
            struct
            {
                uint32_t tbsa : 16; 
 
                uint32_t ndtb  : 6; 
                uint32_t rsvd1 : 2; 
 
                uint32_t tfqs  : 6; 
                uint32_t tfqm  : 1; 
                uint32_t rsvd2 : 1; 
            };
        };
    };
 
    struct Txfqs
    {
        union
        {
            uint32_t data; 
            struct
            {
                uint32_t tffl  : 6; 
                uint32_t rsvd1 : 2; 
 
                uint32_t tfgi  : 5; 
                uint32_t rsvd2 : 3; 
 
                uint32_t tfqpi : 5; 
                uint32_t tfqf  : 1; 
                uint32_t rsvd3 : 2; 
 
                uint32_t rsvd4 : 8; 
            };
        };
    };
 
    struct Txesc
    {
        Txesc()
            : data(0x00000000)
        {
        }
 
        union
        {
            uint32_t data; 
            struct
            {
                uint32_t tbds :  3; 
                uint32_t rsvd : 29; 
            };
        };
    };
 
    struct Txefc
    {
        Txefc()
            : data(0x00000000)
        {
        }
 
        union
        {
            uint32_t data; 
            struct
            {
                uint32_t efsa : 16; 
 
                uint32_t efs   : 6; 
                uint32_t rsvd1 : 2; 
 
                uint32_t efwm  : 6; 
                uint32_t rsvd2 : 2; 
            };
        };
    };
 
    struct Txefs
    {
        union
        {
            uint32_t data; 
            struct
            {
                uint32_t effl  : 6; 
                uint32_t rsvd1 : 2; 
 
                uint32_t efgi : 5; 
                uint32_t rsvd2 : 3; 
 
                uint32_t efpi  : 5; 
                uint32_t rsvd3 : 3; 
 
                uint32_t eff   : 1; 
                uint32_t tefl  : 1; 
                uint32_t rsvd4 : 6; 
            };
        };
    };
 
    struct Txefa
    {
        Txefa()
            : data(0x00000000)
        {
        }
 
        union
        {
            uint32_t data; 
            struct
            {
                uint32_t efai :  5; 
                uint32_t rsvd : 27; 
            };
        };
    };
 
    struct Interrupt
    {
        Interrupt()
            : data(0x00000000)
        {
        }
 
        union
        {
            uint32_t data; 
            struct
            {
                uint32_t vtwd      : 1; 
                uint32_t mcanint   : 1; 
                uint32_t rsvd1     : 1; 
                uint32_t spierr    : 1; 
                uint32_t rsvd2     : 1; 
                uint32_t canerr    : 1; 
                uint32_t wkrq      : 1; 
                uint32_t globalerr : 1; 
 
                uint32_t candom    : 1; 
                uint32_t rsvd3     : 1; 
                uint32_t canslnt   : 1; 
                uint32_t rsvd4     : 2; 
                uint32_t wkerr     : 1; 
                uint32_t lwu       : 1; 
                uint32_t canint    : 1; 
 
                uint32_t eccerr    : 1; 
                uint32_t rsvd5     : 1; 
                uint32_t wdto      : 1; 
                uint32_t tsd       : 1; 
                uint32_t pwron     : 1; 
                uint32_t uvio      : 1; 
                uint32_t uvsup     : 1; 
                uint32_t sms       : 1; 
 
                uint32_t rsvd6     : 7; 
                uint32_t canbusnom : 1; 
            };
        };
    };
 
    struct MCANInterrupt
    {
        MCANInterrupt()
            : data(0x00000000)
        {
        }
 
        union
        {
            uint32_t data; 
            struct
            {
                uint32_t rf0n : 1; 
                uint32_t rf0w : 1; 
                uint32_t rf0f : 1; 
                uint32_t rf0l : 1; 
                uint32_t rf1n : 1; 
                uint32_t rf1w : 1; 
                uint32_t rf1f : 1; 
                uint32_t rf1l : 1; 
 
                uint32_t hpm  : 1; 
                uint32_t tc   : 1; 
                uint32_t tcf  : 1; 
                uint32_t tfe  : 1; 
                uint32_t tefn : 1; 
                uint32_t tefw : 1; 
                uint32_t teff : 1; 
                uint32_t tefl : 1; 
 
                uint32_t tsw  : 1; 
                uint32_t mraf : 1; 
                uint32_t too  : 1; 
                uint32_t drx  : 1; 
                uint32_t bec  : 1; 
                uint32_t beu  : 1; 
                uint32_t elo  : 1; 
                uint32_t ep   : 1; 
 
                uint32_t ew   : 1; 
                uint32_t bo   : 1; 
                uint32_t wdi  : 1; 
                uint32_t pea  : 1; 
                uint32_t ped  : 1; 
                uint32_t ara  : 1; 
                uint32_t rsvd : 2; 
            };
        };
    };
 
    struct Ile
    {
        Ile()
            : data(0x00000000)
        {
        }
 
        union
        {
            uint32_t data; 
            struct
            {
                uint32_t eint0 :  1; 
                uint32_t eint1 :  1; 
                uint32_t rsvd  : 30; 
            };
        };
    };
 
    struct TCAN4550Baud
    {
        uint32_t freq; 
        uint32_t baud; 
        Nbtp     nbtp; 
    };
 
    struct SPIMessage
    {
        union
        {
            uint64_t payload64;    
            uint32_t payload32[2]; 
            uint8_t payload[8];    
            struct
            {
                uint8_t length; 
                uint8_t addrL;  
                uint8_t addrH;  
                union
                {
                    uint8_t cmd;    
                    uint8_t status; 
                };
                uint32_t data;  
            };
        };
    };
 
    struct MRAMSPIMessage
    {
        union
        {
            uint32_t payload32; 
            uint8_t payload[4]; 
            struct
            {
                uint8_t length; 
                uint8_t addrL;  
                uint8_t addrH;  
                union
                {
                    uint8_t cmd;    
                    uint8_t status; 
                };
            };
        };
    };
 
    struct MRAMRXBuffer
    {
        uint32_t id  : 29; 
        uint32_t rtr :  1; 
        uint32_t xtd :  1; 
        uint32_t esi :  1; 
 
        uint32_t rxts : 16; 
        uint32_t dlc  :  4; 
        uint32_t brs  :  1; 
        uint32_t fdf  :  1; 
        uint32_t rsvd :  2; 
        uint32_t fidx :  7; 
        uint32_t anmf :  1; 
 
        union
        {
            uint64_t data64; 
            uint32_t data32[2]; 
            uint16_t data16[4]; 
            uint8_t  data[8]; 
        };
    };
 
    struct MRAMTXBuffer
    {
        uint32_t id  : 29; 
        uint32_t rtr :  1; 
        uint32_t xtd :  1; 
        uint32_t esi :  1; 
 
        uint32_t rsvd1 : 16; 
        uint32_t dlc   :  4; 
        uint32_t brs   :  1; 
        uint32_t fdf   :  1; 
        uint32_t rsvd2 :  1; 
        uint32_t efc   :  1; 
        uint32_t mm    :  8; 
 
        union
        {
            uint64_t data64;  
            uint32_t data32[2]; 
            uint16_t data16[4]; 
        };
    };
 
    struct MRAMTXEventFIFOElement
    {
        uint32_t id  : 29; 
        uint32_t rtr :  1; 
        uint32_t xtd :  1; 
        uint32_t esi :  1; 
 
        uint32_t txts : 16; 
        uint32_t dlc  :  4; 
        uint32_t brs  :  1; 
        uint32_t fdf  :  1; 
        uint32_t et   :  2; 
        uint32_t mm   :  8; 
    };
 
    struct MRAMTXBufferMultiWrite
    {
        static_assert(sizeof(MRAMSPIMessage) == sizeof(uint32_t),
                      "unexpected MRAMSPIMessage size");
 
        uint32_t padding; 
        MRAMSPIMessage header; 
        MRAMTXBuffer txBuffers[TX_FIFO_SIZE]; 
    };
 
    void flush_buffers() override;
 
    ssize_t read(File *file, void *buf, size_t count) override;
 
    ssize_t write(File *file, const void *buf, size_t count) override;
 
    int ioctl(File *file, unsigned long int key, unsigned long data) override;
 
    bool select(File* file, int mode) override;
 
    void *entry() override;
 
    void enable() override; 
    void disable() override; 
 
    void tx_msg() override
    {
        // unused in this implementation
    }
 
    __attribute__((optimize("-O3")))
    uint32_t register_read(Registers address)
    {
        SPIMessage msg;
        msg.cmd = READ;
        msg.addrH = address >> 6;
        msg.addrL = (address << 2) & 0xFF;
        msg.length = 1;
 
        spi_ioc_transfer xfer;
        xfer.tx_buf = (unsigned long)(&msg);
        xfer.rx_buf = (unsigned long)(&msg);
        xfer.len = sizeof(msg);
 
        spi_->transfer_with_cs_assert_polled(&xfer);
 
#if TCAN4550_DEBUG
        HASSERT((msg.status & 0x8) == 0);
#endif
 
        return msg.data;
    }
 
    __attribute__((optimize("-O3")))
    void register_write(Registers address, uint32_t data)
    {
        SPIMessage msg;
        msg.cmd = WRITE;
        msg.addrH = address >> 6;
        msg.addrL = (address << 2) & 0xFF;
        msg.length = 1;
        msg.data = data;
 
        spi_ioc_transfer xfer;
        xfer.tx_buf = (unsigned long)(&msg);
        xfer.rx_buf = (unsigned long)(&msg);
        xfer.len = sizeof(msg);
 
        spi_->transfer_with_cs_assert_polled(&xfer);
#if TCAN4550_DEBUG
        HASSERT((msg.status & 0x8) == 0);
#endif
    }
 
    __attribute__((optimize("-O3")))
    void rxbuf_read(uint16_t offset, MRAMRXBuffer *buf, size_t count)
    {
        uint16_t address = offset + MRAM_ADDR_OFFSET;
        SPIMessage msg;
        msg.cmd = READ;
        msg.addrH = address >> 8;
        msg.addrL = address & 0xFF;
        msg.length = count * (sizeof(MRAMRXBuffer) / 4);
 
        spi_ioc_transfer xfer[2];
        xfer[0].tx_buf = (unsigned long)(&msg);
        xfer[0].rx_buf = (unsigned long)(&msg);
        xfer[0].len = 4; //sizeof(SPIMessage);
        xfer[1].tx_buf = (unsigned long)(nullptr);
        xfer[1].rx_buf = (unsigned long)(buf);
        xfer[1].len = count * sizeof(MRAMRXBuffer);
 
        spi_->transfer_with_cs_assert_polled(xfer, 2);
#if TCAN4550_DEBUG
        HASSERT((msg.status & 0x8) == 0);
#endif
    }
 
    __attribute__((optimize("-O3")))
    void txbuf_write(uint16_t offset, MRAMTXBufferMultiWrite *buf, size_t count)
    {
        static_assert(sizeof(MRAMTXBuffer) == 16,
                      "Unexpected MRAMTXBuffer size");
 
        uint16_t address = offset + MRAM_ADDR_OFFSET;
        buf->header.cmd = WRITE;
        buf->header.addrH = address >> 8;
        buf->header.addrL = address & 0xFF;
        buf->header.length = count * (sizeof(MRAMTXBuffer) / 4);
 
        spi_ioc_transfer xfer;
        xfer.tx_buf = (unsigned long)&buf->header;
        xfer.rx_buf = (unsigned long)&buf->header;
        xfer.len = sizeof(buf->header) + (count * sizeof(MRAMTXBuffer));
 
        spi_->transfer_with_cs_assert_polled(&xfer);
#if TCAN4550_DEBUG
        HASSERT((buf->header.status & 0x8) == 0);
#endif
    }
 
    void (*interruptEnable_)(); 
    void (*interruptDisable_)(); 
    int spiFd_; 
    SPI *spi_; 
    OSSem sem_; 
    MCANInterrupt mcanInterruptEnable_; 
    uint32_t txCompleteMask_; 
    uint8_t state_; 
 
    // These bitmasks are protected from a read-modify-write race condition
    // because they are only set from a thread context that holds the SPI bus
    // mutex.
    uint8_t txPending_ : 1; 
    uint8_t rxPending_ : 1; 
 
    MRAMTXBufferMultiWrite txBufferMultiWrite_ __attribute__((aligned(8)));
#if TCAN4550_DEBUG
    volatile uint32_t regs_[64]; 
    volatile uint32_t status_;
    volatile uint32_t enable_;
    volatile uint32_t spiStatus_;
    const Gpio *testPin_; 
#endif
 
    static const TCAN4550Baud BAUD_TABLE[];
 
    TCAN4550Can();
 
    DISALLOW_COPY_AND_ASSIGN(TCAN4550Can);
};
 
#endif // _FREERTOS_DRIVERS_COMMON_TCAN4550CAN_HXX_