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Open Model Railroad Network (OpenMRN)
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#include "Can.hxx"#include "DummyGPIO.hxx"#include "SPI.hxx"#include "os/Gpio.hxx"#include "os/OS.hxx"#include "utils/Atomic.hxx"#include "can_ioctl.h"Go to the source code of this file.
Classes | |
| class | TCAN4550Can |
| Specification of CAN driver for the TCAN4550. More... | |
| struct | TCAN4550Can::Mode |
| Mode register definition. More... | |
| struct | TCAN4550Can::Dbtp |
| Data bit timing and prescaler register definition. More... | |
| struct | TCAN4550Can::Cccr |
| CC control register definition. More... | |
| struct | TCAN4550Can::Nbtp |
| Nominal bit timing & prescaler register definition. More... | |
| struct | TCAN4550Can::Tscc |
| Timestamp counter configuration register definition. More... | |
| struct | TCAN4550Can::Tscv |
| Timestamp counter value register definition. More... | |
| struct | TCAN4550Can::Tocc |
| Timeout counter configuration register definition. More... | |
| struct | TCAN4550Can::Tocv |
| Timeout counter value register definition. More... | |
| struct | TCAN4550Can::Psr |
| Protocol status register definition. More... | |
| struct | TCAN4550Can::Rxfxc |
| RX FIFO x configuraation register definition. More... | |
| struct | TCAN4550Can::Rxfxs |
| RX FIFO x status register definition. More... | |
| struct | TCAN4550Can::Rxfxa |
| RX FIFO x acknowledge register definition. More... | |
| struct | TCAN4550Can::Txbc |
| TX Buffer configuraation register definition. More... | |
| struct | TCAN4550Can::Txfqs |
| TX FIFO/queue status register definition. More... | |
| struct | TCAN4550Can::Txesc |
| TX buffer element size configurataion register definition. More... | |
| struct | TCAN4550Can::Txefc |
| TX event FIFO configuration register definition. More... | |
| struct | TCAN4550Can::Txefs |
| TX event FIFO status register definition. More... | |
| struct | TCAN4550Can::Txefa |
| TX event FIFO acknowledge register definition. More... | |
| struct | TCAN4550Can::Interrupt |
| TCAN4550 interrupt registers (INTERRUPT_ENABLE/STATUS) More... | |
| struct | TCAN4550Can::MCANInterrupt |
| MCAN interrupt registers (IR, IE, and ILS) definition. More... | |
| struct | TCAN4550Can::Ile |
| MCAN interrupt line enable register definition. More... | |
| struct | TCAN4550Can::TCAN4550Baud |
| Buad rate table entry. More... | |
| struct | TCAN4550Can::SPIMessage |
| SPI message for read/write commands. More... | |
| struct | TCAN4550Can::MRAMSPIMessage |
| MRAM SPI message for read/write commands. More... | |
| struct | TCAN4550Can::MRAMRXBuffer |
| RX Buffer structure. More... | |
| struct | TCAN4550Can::MRAMTXBuffer |
| TX Buffer structure. More... | |
| struct | TCAN4550Can::MRAMTXEventFIFOElement |
| TX Event FIFO Element structure. More... | |
| struct | TCAN4550Can::MRAMTXBufferMultiWrite |
| Structure for writing multiple TX buffers in one SPI transaction. More... | |
Macros | |
| #define | TCAN4550_DEBUG 0 |
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
This file implements the CAN driver for the TCAN4550 CAN Controller.
Definition in file TCAN4550Can.hxx.
| #define TCAN4550_DEBUG 0 |
Definition at line 47 of file TCAN4550Can.hxx.