RailcomImpl.hxx

 
#ifndef _FREERTOS_DRIVERS_COMMON_RAILCOMIMPL_HXX_
#define _FREERTOS_DRIVERS_COMMON_RAILCOMIMPL_HXX_
 
#include "freertos_drivers/common/RailcomDriver.hxx"
#include "freertos_drivers/common/FixedQueue.hxx"
#include "dcc/RailCom.hxx"
 
/*
struct RailcomHw
{
    static const uint32_t CHANNEL_COUNT = 4;
    static const uint32_t UART_PERIPH[CHANNEL_COUNT];
    static const uint32_t UART_BASE[CHANNEL_COUNT];
    // Make sure there are enough entries here for all the channels times a few
    // DCC packets.
    static const uint32_t Q_SIZE = 16;
 
    static const auto OS_INTERRUPT = INT_UART2;
 
    GPIO_HWPIN(CH1, GpioHwPin, C, 4, U4RX);
    GPIO_HWPIN(CH2, GpioHwPin, C, 6, U3RX);
    GPIO_HWPIN(CH3, GpioHwPin, G, 4, U2RX);
    GPIO_HWPIN(CH4, GpioHwPin, E, 0, U7RX);
 
    static void hw_init() {
         CH1_Pin::hw_init();
         CH2_Pin::hw_init();
         CH3_Pin::hw_init();
         CH4_Pin::hw_init();
    }
 
    static void set_input() {
        CH1_Pin::set_input();
        CH2_Pin::set_input();
        CH3_Pin::set_input();
        CH4_Pin::set_input();
    }
 
    static void set_hw() {
        CH1_Pin::set_hw();
        CH2_Pin::set_hw();
        CH3_Pin::set_hw();
        CH4_Pin::set_hw();
    }
 
    static uint8_t sample() {
        uint8_t ret = 0;
        if (!CH1_Pin::get()) ret |= 1;
        if (!CH2_Pin::get()) ret |= 2;
        if (!CH3_Pin::get()) ret |= 4;
        if (!CH4_Pin::get()) ret |= 8;
        return ret;
    }
}; 
 
// The weak attribute is needed if the definition is put into a header file.
const uint32_t RailcomHw::UART_BASE[] __attribute__((weak)) = {UART4_BASE, UART3_BASE, UART2_BASE, UART7_BASE};
const uint32_t RailcomHw::UART_PERIPH[]
__attribute__((weak)) = {SYSCTL_PERIPH_UART4, SYSCTL_PERIPH_UART3, SYSCTL_PERIPH_UART2, SYSCTL_PERIPH_UART7};
 
*/
 
template <class HW>
class RailcomDriverBase : public RailcomDriver, private Node
{
public:
    RailcomDriverBase(const char *name)
        : Node(name)
        , readableNotifiable_(nullptr)
    {
        HW::hw_init();
    }
 
    ~RailcomDriverBase()
    {
    }
 
private:
    virtual void int_set_pending(unsigned int_nr) = 0;
    
    ssize_t write(File *, const void *, size_t) OVERRIDE
    {
        // This device is read-only.
        return -ENOSYS;
    }
 
    ssize_t read(File *file, void *buf, size_t count) OVERRIDE
    {
        if (count != sizeof(dcc::Feedback))
        {
            return -EINVAL;
        }
        OSMutexLock l(&lock_);
        if (feedbackQueue_.empty())
        {
            return -EAGAIN;
        }
        memcpy(buf, &feedbackQueue_.front(), count);
        feedbackQueue_.increment_front();
        return count;
    }
 
    void flush_buffers() OVERRIDE
    {
        while (!feedbackQueue_.empty())
        {
            feedbackQueue_.increment_front();
        }
    }
 
    // Asynchronous interface
    int ioctl(File *file, unsigned long int key, unsigned long data) override
    {
        if (IOC_TYPE(key) == CAN_IOC_MAGIC &&
            IOC_SIZE(key) == NOTIFIABLE_TYPE && key == CAN_IOC_READ_ACTIVE)
        {
            Notifiable *n = reinterpret_cast<Notifiable *>(data);
            HASSERT(n);
            // If there is no data for reading, we put the incoming notification
            // into the holder. Otherwise we notify it immediately.
            if (feedbackQueue_.empty())
            {
                portENTER_CRITICAL();
                if (feedbackQueue_.empty())
                {
                    // We are in a critical section now. If we got into this
                    // branch, then the buffer was full at the beginning of the
                    // critical section. If the hardware interrupt kicks in
                    // now, and sets the os_interrupt to pending, the os
                    // interrupt will not happen until we leave the critical
                    // section, and thus the swap will be in effect by then.
                    std::swap(n, readableNotifiable_);
                }
                portEXIT_CRITICAL();
            }
            if (n)
            {
                n->notify();
            }
            return 0;
        }
        errno = EINVAL;
        return -1;
    }
 
public:
    void os_interrupt_handler() __attribute__((always_inline))
    {
        if (!feedbackQueue_.empty())
        {
            Notifiable *n = readableNotifiable_;
            readableNotifiable_ = nullptr;
            if (n)
            {
                n->notify_from_isr();
                os_isr_exit_yield_test(true);
            }
        }
    }
 
private:
    void set_feedback_key(uint32_t key) OVERRIDE
    {
        feedbackKey_ = key;
    }
 
protected:
    dcc::Feedback *alloc_new_packet(uint8_t channel)
    {
        if (!feedbackQueue_.has_noncommit_space())
        {
            return nullptr;
        }
        dcc::Feedback *entry = &feedbackQueue_.back();
        feedbackQueue_.noncommit_back();
        entry->reset(feedbackKey_);
        entry->channel = channel;
        return entry;
    }
 
    void add_sample(int sample) {
        if (sample < 0) return; // skipped sampling
        if (feedbackQueue_.full()) {
            extern uint32_t feedback_sample_overflow_count;
            ++feedback_sample_overflow_count;
            return;
        }
        feedbackQueue_.back().reset(feedbackKey_);
        feedbackQueue_.back().channel = HW::get_feedback_channel();
        feedbackQueue_.back().add_ch1_data(sample);
        uint32_t tick_timer = HW::get_timer_tick();
        memcpy(feedbackQueue_.back().ch2Data, &tick_timer, 4);
        feedbackQueue_.increment_back();
        int_set_pending(HW::OS_INTERRUPT);
    }
 
    Notifiable *readableNotifiable_;
    FixedQueue<dcc::Feedback, HW::Q_SIZE> feedbackQueue_;
    uint32_t feedbackKey_;
    dcc::Feedback *returnedPackets_[HW::CHANNEL_COUNT];
};
 
#endif // _FREERTOS_DRIVERS_COMMON_RAILCOMIMPL_HXX_