CC32xxSPI.hxx

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#ifndef _FREERTOS_DRIVERS_TI_CC32XXSPI_HXX_
#define _FREERTOS_DRIVERS_TI_CC32XXSPI_HXX_
 
#ifndef gcc
#define gcc
#endif
 
#include <cstdint>
 
#include "SPI.hxx"
 
#include "inc/hw_mcspi.h"
#include "inc/hw_types.h"
#include "driverlib/udma.h"
 
#include <ti/drivers/dma/UDMACC32XX.h>
 
class CC32xxSPI : public SPI, private Atomic
{
public:
    CC32xxSPI(const char *name, unsigned long base, uint32_t interrupt,
            ChipSelectMethod cs_assert, ChipSelectMethod cs_deassert,
            OSMutex *bus_lock = nullptr,
            size_t dma_threshold = DEFAULT_DMA_THRESHOLD_BYTES,
            uint32_t dma_channel_index_tx = UDMA_CH7_GSPI_TX,
            uint32_t dma_channel_index_rx = UDMA_CH6_GSPI_RX);
 
    ~CC32xxSPI()
    {
    }
 
    void interrupt_handler();
 
    OSMutex *get_lock()
    {
        return &lock_;
    }
 
private:
    static constexpr size_t DEFAULT_DMA_THRESHOLD_BYTES = 64;
 
    static constexpr size_t MAX_DMA_TRANSFER_AMOUNT = 1024;
 
    static constexpr uint32_t dmaRxConfig_[] =
    {
        UDMA_SIZE_8  | UDMA_SRC_INC_NONE | UDMA_DST_INC_8  | UDMA_ARB_1,
        UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 | UDMA_ARB_1,
        UDMA_SIZE_32 | UDMA_SRC_INC_NONE | UDMA_DST_INC_32 | UDMA_ARB_1
    };
 
    static constexpr uint32_t dmaTxConfig_[] =
    {
        UDMA_SIZE_8  | UDMA_SRC_INC_8  | UDMA_DST_INC_NONE | UDMA_ARB_1,
        UDMA_SIZE_16 | UDMA_SRC_INC_16 | UDMA_DST_INC_NONE | UDMA_ARB_1,
        UDMA_SIZE_32 | UDMA_SRC_INC_32 | UDMA_DST_INC_NONE | UDMA_ARB_1
    };
 
    static constexpr uint32_t dmaNullConfig_[] =
    {
        UDMA_SIZE_8  | UDMA_SRC_INC_NONE | UDMA_DST_INC_NONE | UDMA_ARB_1,
        UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_NONE | UDMA_ARB_1,
        UDMA_SIZE_32 | UDMA_SRC_INC_NONE | UDMA_DST_INC_NONE | UDMA_ARB_1
    };
 
    void enable() override
    {
        dmaHandle_ = UDMACC32XX_open();
    }
 
    void disable() override
    {
        UDMACC32XX_close(dmaHandle_);
    }
 
    int update_configuration() override;
 
    __attribute__((optimize("-O3")))
    int transfer(struct spi_ioc_transfer *msg) override
    {
        if (LIKELY(msg->len < dmaThreshold_))
        {
            return transfer_polled(msg);
        }
        else
        {
            /* use DMA */
            config_dma(msg);
        }
 
        return msg->len;
    }
 
    template<typename T>
    __attribute__((optimize("-O3")))
    int transfer_polled(struct spi_ioc_transfer *msg)
    {
        T dummy = 0;
 
        /* we are assuming that at least one byte will be transferred, and
         * we want to start tranfering data as soon as possible
         */
        data_put(msg->tx_buf ? *((T*)msg->tx_buf) : 0xFFFFFFFF);
 
        T *tx_buf = msg->tx_buf ? ((T*)msg->tx_buf) + 1 : &dummy;
        T *rx_buf = (T*)msg->rx_buf;
 
        /* note that we already have transmitted one SPI word above, hence the
         * subtract one from the tx_len
         */
        uint32_t rx_len = msg->len / sizeof(T);
        uint32_t tx_len = rx_len - 1;
 
        unsigned long data;
 
        do
        {
            /* fill TX FIFO but make sure we don't fill it to overflow */
            if (tx_len && ((rx_len - tx_len) < (32 / sizeof(T))))
            {
                if (data_put_non_blocking(*tx_buf) != 0)
                {
                    if (msg->tx_buf)
                    {
                        ++tx_buf;
                    }
                    --tx_len;
                }
            }
 
            /* empty RX FIFO */
            if (rx_len)
            {
                if (data_get_non_blocking(&data) != 0)
                {
                    if (msg->rx_buf)
                    {
                        *rx_buf++ = data;
                    }
                    --rx_len;
                }
            }
        }
        while (tx_len || rx_len);
 
        return msg->len;
    }
 
    __attribute__((optimize("-O3")))
    int transfer_polled(struct spi_ioc_transfer *msg) override
    {
        /* set instance specific configuration */
        set_configuration();
 
        switch (bitsPerWord)
        {
            default:
            case 8:
                return transfer_polled<uint8_t>(msg);
            case 16:
                return transfer_polled<uint16_t>(msg);
            case 32:
                return transfer_polled<uint32_t>(msg);
        }
    }
 
    void config_dma(struct spi_ioc_transfer *msg);
 
    __attribute__((optimize("-O3")))
    long data_get_non_blocking(unsigned long *data)
    {
        if(HWREG(base_ + MCSPI_O_CH0STAT) & MCSPI_CH0STAT_RXS)
        {
            *data = HWREG(base_ + MCSPI_O_RX0);
            return 1;
        }
 
        return 0;
    }
 
    __attribute__((optimize("-O3")))
    long data_put_non_blocking(unsigned long data)
    {
        if(HWREG(base_ + MCSPI_O_CH0STAT) & MCSPI_CH0STAT_TXS)
        {
            HWREG(base_ + MCSPI_O_TX0) = data;
            return 1;
        }
 
        return 0;
    }
 
    void data_put(unsigned long data)
    {
        while(UNLIKELY(!(HWREG(base_ + MCSPI_O_CH0STAT)&MCSPI_CH0STAT_TXS)));
 
        HWREG(base_ + MCSPI_O_TX0) = data;
    }
 
    void set_configuration()
    {
        HWREG(base_ + MCSPI_O_CH0CTRL) = spiChctrl_;
        HWREG(base_ + MCSPI_O_CH0CONF) = spiChconf_;
        HWREG(base_ + MCSPI_O_XFERLEVEL) = spiXferlevel_;
    }
 
    UDMACC32XX_Handle dmaHandle_; 
    OSSem *sem_; 
    unsigned long base_; 
    unsigned long clock_; 
    unsigned long interrupt_; 
    size_t dmaThreshold_; 
    uint32_t dmaChannelIndexTx_; 
    uint32_t dmaChannelIndexRx_; 
    uint32_t spiChctrl_; 
    uint32_t spiChconf_; 
    uint32_t spiXferlevel_; 
    CC32xxSPI();
 
    DISALLOW_COPY_AND_ASSIGN(CC32xxSPI);
};
 
#endif /* _FREERTOS_DRIVERS_TI_CC32XXSPI_HXX_ */