TivaI2C.cxx

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#include <algorithm>
 
#include <stdint.h>
 
#include "inc/hw_types.h"
#include "inc/hw_memmap.h"
#include "inc/hw_ints.h"
#include "inc/hw_i2c.h"
#include "driverlib/rom.h"
#include "driverlib/rom_map.h"
#include "driverlib/i2c.h"
#include "driverlib/interrupt.h"
#include "driverlib/sysctl.h"
 
#include "TivaDev.hxx"
 
TivaI2C::TivaI2C(const char *name, unsigned long base, uint32_t interrupt, bool fast_mode)
    : I2C(name)
    , base(base)
    , interrupt(interrupt)
    , msg_(NULL)
    , stop_(false)
    , count_(0)
    , sem()
{
    switch (base)
    {
        default:
            HASSERT(0);
        case I2C0_BASE:
            MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C0);
            break;
        case I2C1_BASE:
            MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C1);
            break;
        case I2C2_BASE:
            MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C2);
            break;
        case I2C3_BASE:
            MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C3);
            break;
        case I2C4_BASE:
            MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C4);
            break;
        case I2C5_BASE:
            MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C5);
            break;
        case I2C6_BASE:
            MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C6);
            break;
        case I2C7_BASE:
            MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C7);
            break;
        case I2C8_BASE:
            MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C8);
            break;
        case I2C9_BASE:
            MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C9);
            break;
    }
 
    /* default to 100 KHz mode */
    MAP_I2CMasterInitExpClk(base, cm3_cpu_clock_hz, fast_mode);
 
    /* We set the priority so that it is slightly lower than the highest needed
     * for FreeRTOS compatibility. This will ensure that CAN interrupts take
     * precedence over UART. */
    MAP_IntPrioritySet(interrupt,
                       std::min(0xff, configKERNEL_INTERRUPT_PRIORITY + 0x20));
    MAP_I2CMasterIntEnableEx(base, I2C_MASTER_INT_TIMEOUT |
                                   I2C_MASTER_INT_DATA);
}
 
int TivaI2C::transfer(struct i2c_msg *msg, bool stop)
{
    int bytes = msg->len;
 
    if (msg->flags & I2C_M_RD)
    {
        /* this is a read transfer */
            MAP_I2CMasterSlaveAddrSet(base, msg->addr, true);
 
        /* generate start */
        if (stop && msg->len == 1)
        {
            /* single byte transfer with stop */
            MAP_I2CMasterControl(base, I2C_MASTER_CMD_SINGLE_RECEIVE);
        }
        else
        {
            /* more than one byte to transfer */
            MAP_I2CMasterControl(base, I2C_MASTER_CMD_BURST_RECEIVE_START);
        }
    }
    else
    {
        /* this is a write transfer */
            MAP_I2CMasterSlaveAddrSet(base, msg->addr, false);
        MAP_I2CMasterDataPut(base, *msg->buf);
 
        /* generate start */
        if (stop && msg->len == 1)
        {
            /* single byte transfer with stop */
            MAP_I2CMasterControl(base, I2C_MASTER_CMD_SINGLE_SEND);
        }
        else
        {
            /* more than one byte to transfer */
            MAP_I2CMasterControl(base, I2C_MASTER_CMD_BURST_SEND_START);
        }
    }
 
    msg_ = msg;
    count_ = 0;
    stop_ = stop;
    
    MAP_IntEnable(interrupt);
    sem.wait();
 
    return count_ < 0 ? count_ : bytes;    
}
 
volatile uint32_t g_error;
volatile uint32_t g_status;
 
void TivaI2C::interrupt_handler()
{
    int woken = 0;
    uint32_t error;
    uint32_t status;
 
    g_error = error = I2CMasterErr(base);
    g_status = status = MAP_I2CMasterIntStatusEx(base, true);
    MAP_I2CMasterIntClearEx(base, status);
 
    if (error & I2C_MCS_ARBLST)
    {
        count_ = -EIO;
        goto post;
    }
    else if (error & I2C_MCS_DATACK)
    {
        count_ = -EIO;
        goto post;
    }
    else if (error & I2C_MCS_ADRACK)
    {
        count_ = -EIO;
        goto post;
    }
    else if (status & I2C_MASTER_INT_TIMEOUT)
    {
        count_ = -ETIMEDOUT;
        goto post;
    }
    else if (status & I2C_MASTER_INT_DATA)
    {
        if (msg_->flags & I2C_M_RD)
        {
            /* this is a read transfer */
            msg_->buf[count_++] = I2CMasterDataGet(base);
            if (count_ == msg_->len)
            {
                /* transfer is complete */
                goto post;
            }
            if (stop_ && count_ == (msg_->len - 1))
            {
                /* single byte transfer with stop */
                MAP_I2CMasterControl(base, I2C_MASTER_CMD_BURST_RECEIVE_FINISH);
            }
            else
            {
                /* more than one byte left to transfer */
                MAP_I2CMasterControl(base, I2C_MASTER_CMD_BURST_RECEIVE_CONT);
            }
        }
        else
        {
            /* this is a write transfer */
            if (++count_ == msg_->len)
            {
                /* transfer is complete */
                goto post;
            }
            MAP_I2CMasterDataPut(base, msg_->buf[count_]);
            if (stop_ && count_ == (msg_->len - 1))
            {
                /* single byte transfer with stop */
                MAP_I2CMasterControl(base, I2C_MASTER_CMD_BURST_SEND_FINISH);
            }
            else
            {
                /* more than one byte left to transfer */
                MAP_I2CMasterControl(base, I2C_MASTER_CMD_BURST_SEND_CONT);
            }
        }
        return;
    }
    else// if (error)
    {
        count_ = -EIO;
        goto post;
    }
/*    else
    {
        // should never get here
        HASSERT(0 && "I2C invalid status");
        }*/
post:
    MAP_IntDisable(interrupt);
    sem.post_from_isr(&woken);
    os_isr_exit_yield_test(woken);
}