TivaDCCDecoder.hxx

 
#include "TivaDCC.hxx"  // for FixedQueue
#include "TivaGPIO.hxx" // for pin definitions
#include "freertos_drivers/common/DccDecoder.hxx"
 
typedef DummyPin PIN_RailcomCutout;
 
template <class HW> class TivaDccTimerModule
{
public:
    using NRZ_Pin = typename HW::NRZ_Pin;
 
    // These constants are exported from HW to the driver.
 
    static constexpr uint32_t TIMER_MAX_VALUE = HW::TIMER_MAX_VALUE;
    static constexpr uint32_t SAMPLE_PERIOD_CLOCKS = HW::SAMPLE_PERIOD_CLOCKS;
    static constexpr unsigned Q_SIZE = HW::Q_SIZE;
 
    static uint32_t get_ticks_per_usec()
    {
        return configCPU_CLOCK_HZ / 1000000;
    }
 
    static void module_init();
 
    static void module_enable();
 
    static void module_disable();
 
    static void trigger_os_interrupt()
    {
        MAP_IntPendSet(HW::OS_INTERRUPT);
    }
 
    static void dcc_before_cutout_hook()
    {
        HW::dcc_before_cutout_hook();
    }
 
    static void dcc_packet_finished_hook()
    {
        HW::dcc_packet_finished_hook();
    }
 
    static void after_feedback_hook()
    {
        HW::after_feedback_hook();
    }
 
    static int time_delta_railcom_pre_usec()
    {
        return HW::time_delta_railcom_pre_usec();
    }
 
    static int time_delta_railcom_mid_usec()
    {
        return HW::time_delta_railcom_mid_usec();
    }
 
    static int time_delta_railcom_end_usec()
    {
        return HW::time_delta_railcom_end_usec();
    }
    
    static inline bool int_get_and_clear_capture_event();
 
    static inline uint32_t get_capture_counter();
 
    static inline bool int_get_and_clear_delay_event();
 
    static void set_cap_timer_delay_usec(int usec)
    {
        Debug::DccPacketDelay::toggle();
        uint32_t new_match_v = usec * 80;
        MAP_TimerMatchSet(HW::TIMER_BASE, HW::RCOM_TIMER, 0xfffe - new_match_v);
        MAP_TimerPrescaleMatchSet(HW::TIMER_BASE, HW::RCOM_TIMER, 0);
    }
 
    static void set_cap_timer_capture()
    {
        MAP_TimerDisable(HW::TIMER_BASE, HW::TIMER);
        MAP_TimerIntDisable(
            HW::TIMER_BASE, HW::TIMER_CAP_EVENT);
        MAP_TimerIntClear(
            HW::TIMER_BASE, HW::TIMER_CAP_EVENT);
 
        MAP_TimerConfigure(
            HW::TIMER_BASE, HW::CFG_TIM_CAPTURE | HW::CFG_RCOM_TIMER);
        MAP_TimerControlEvent(
            HW::TIMER_BASE, HW::TIMER, TIMER_EVENT_BOTH_EDGES);
        MAP_TimerLoadSet(HW::TIMER_BASE, HW::TIMER, HW::TIMER_MAX_VALUE);
        MAP_TimerPrescaleSet(HW::TIMER_BASE, HW::TIMER, HW::PS_MAX);
 
        MAP_TimerIntEnable(HW::TIMER_BASE, HW::TIMER_CAP_EVENT);
        MAP_TimerEnable(HW::TIMER_BASE, HW::TIMER);
    }
 
    static void set_cap_timer_time()
    {
        MAP_TimerDisable(HW::TIMER_BASE, HW::RCOM_TIMER);
 
        MAP_TimerIntDisable(
            HW::TIMER_BASE, HW::TIMER_RCOM_MATCH);
        MAP_TimerIntClear(
            HW::TIMER_BASE, HW::TIMER_RCOM_MATCH);
        HW::clr_tim_mrsu();
        MAP_TimerLoadSet(HW::TIMER_BASE, HW::RCOM_TIMER, 0xfffe);
        MAP_TimerPrescaleSet(HW::TIMER_BASE, HW::RCOM_TIMER, 0);
 
        MAP_TimerIntEnable(HW::TIMER_BASE, HW::TIMER_RCOM_MATCH);
        MAP_TimerEnable(HW::TIMER_BASE, HW::RCOM_TIMER);
    }
 
    static void stop_cap_timer_time()
    {
        MAP_TimerDisable(HW::TIMER_BASE, HW::RCOM_TIMER);
    }
 
    DISALLOW_COPY_AND_ASSIGN(TivaDccTimerModule);
};
 
template <class HW> void TivaDccTimerModule<HW>::module_init()
{
    MAP_SysCtlPeripheralEnable(HW::TIMER_PERIPH);
    MAP_GPIOPadConfigSet(HW::NRZ_Pin::GPIO_BASE, HW::NRZ_Pin::GPIO_PIN,
                         GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU);
}
 
template <class HW> void TivaDccTimerModule<HW>::module_enable()
{
    MAP_TimerClockSourceSet(HW::TIMER_BASE, TIMER_CLOCK_SYSTEM);
    MAP_TimerControlStall(HW::TIMER_BASE, HW::TIMER, true);
 
    set_cap_timer_capture();
 
    MAP_TimerIntEnable(HW::TIMER_BASE, HW::TIMER_CAP_EVENT);
 
    MAP_IntPrioritySet(HW::TIMER_INTERRUPT, 0x20);
    MAP_IntPrioritySet(HW::RCOM_INTERRUPT, 0x20);
    MAP_IntPrioritySet(HW::OS_INTERRUPT, configKERNEL_INTERRUPT_PRIORITY);
    MAP_IntEnable(HW::OS_INTERRUPT);
    MAP_IntEnable(HW::TIMER_INTERRUPT);
    MAP_IntEnable(HW::RCOM_INTERRUPT);
}
 
template <class HW> void TivaDccTimerModule<HW>::module_disable()
{
    MAP_IntDisable(HW::TIMER_INTERRUPT);
    MAP_IntDisable(HW::RCOM_INTERRUPT);
    MAP_IntDisable(HW::OS_INTERRUPT);
    MAP_TimerDisable(HW::TIMER_BASE, HW::TIMER);
    MAP_TimerDisable(HW::TIMER_BASE, HW::RCOM_TIMER);
}
 
template <class HW>
bool TivaDccTimerModule<HW>::int_get_and_clear_capture_event()
{
    // get masked interrupt status
    auto status = MAP_TimerIntStatus(HW::TIMER_BASE, true);
    if (status & HW::TIMER_CAP_EVENT)
    {
        //Debug::DccDecodeInterrupts::toggle();
        HW::cap_event_hook();
        MAP_TimerIntClear(HW::TIMER_BASE, HW::TIMER_CAP_EVENT);
        return true;
    }
    return false;
}
 
template <class HW> uint32_t TivaDccTimerModule<HW>::get_capture_counter()
{
    return MAP_TimerValueGet(HW::TIMER_BASE, HW::TIMER);
}
 
template <class HW> bool TivaDccTimerModule<HW>::int_get_and_clear_delay_event()
{
    Debug::DccDecodeInterrupts::set(true);
    auto status = MAP_TimerIntStatus(HW::TIMER_BASE, true);
    if (status & HW::TIMER_RCOM_MATCH)
    {
        MAP_TimerIntClear(HW::TIMER_BASE, HW::TIMER_RCOM_MATCH);
        return true;
    }
    return false;
}
 
template <class HW> using TivaDccDecoder = DccDecoder<TivaDccTimerModule<HW>>;