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lpc23xx.h
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/*****************************************************************************
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*
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* Project : lwIP Web
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* Subproject :
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* Name : LPC23xx.h
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* Function : register definitions
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* Designer : K. Sterckx
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* Creation date : 22/01/2007
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* Compiler : GNU ARM
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* Processor : LPC23xx
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* Last update :
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* Last updated by :
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* History :
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*
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*****************************************************************************
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*
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* Hardware specific macro's and defines
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*
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****************************************************************************/
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#ifndef __LPC23xx_H
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#define __LPC23xx_H
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/* Vectored Interrupt Controller (VIC) */
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#define VIC_BASE_ADDR 0xFFFFF000
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#define VICIRQStatus (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x000))
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#define VICFIQStatus (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x004))
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#define VICRawIntr (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x008))
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#define VICIntSelect (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x00C))
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#define VICIntEnable (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x010))
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#define VICIntEnClr (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x014))
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#define VICSoftInt (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x018))
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#define VICSoftIntClr (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x01C))
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#define VICProtection (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x020))
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#define VICSWPrioMask (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x024))
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#define VICVectAddr0 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x100))
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#define VICVectAddr1 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x104))
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#define VICVectAddr2 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x108))
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#define VICVectAddr3 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x10C))
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#define VICVectAddr4 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x110))
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#define VICVectAddr5 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x114))
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#define VICVectAddr6 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x118))
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#define VICVectAddr7 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x11C))
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#define VICVectAddr8 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x120))
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#define VICVectAddr9 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x124))
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#define VICVectAddr10 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x128))
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#define VICVectAddr11 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x12C))
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#define VICVectAddr12 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x130))
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#define VICVectAddr13 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x134))
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#define VICVectAddr14 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x138))
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#define VICVectAddr15 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x13C))
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#define VICVectAddr16 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x140))
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#define VICVectAddr17 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x144))
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#define VICVectAddr18 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x148))
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#define VICVectAddr19 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x14C))
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#define VICVectAddr20 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x150))
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#define VICVectAddr21 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x154))
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#define VICVectAddr22 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x158))
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#define VICVectAddr23 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x15C))
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#define VICVectAddr24 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x160))
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#define VICVectAddr25 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x164))
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#define VICVectAddr26 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x168))
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#define VICVectAddr27 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x16C))
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#define VICVectAddr28 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x170))
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#define VICVectAddr29 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x174))
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#define VICVectAddr30 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x178))
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#define VICVectAddr31 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x17C))
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/* The name convention below is from previous LPC2000 family MCUs, in LPC230x,
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these registers are known as "VICVectPriority(x)". */
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#define VICVectCntl0 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x200))
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#define VICVectCntl1 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x204))
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#define VICVectCntl2 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x208))
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#define VICVectCntl3 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x20C))
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#define VICVectCntl4 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x210))
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#define VICVectCntl5 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x214))
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#define VICVectCntl6 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x218))
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#define VICVectCntl7 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x21C))
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#define VICVectCntl8 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x220))
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#define VICVectCntl9 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x224))
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#define VICVectCntl10 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x228))
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#define VICVectCntl11 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x22C))
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#define VICVectCntl12 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x230))
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#define VICVectCntl13 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x234))
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#define VICVectCntl14 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x238))
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#define VICVectCntl15 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x23C))
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#define VICVectCntl16 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x240))
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#define VICVectCntl17 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x244))
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#define VICVectCntl18 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x248))
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#define VICVectCntl19 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x24C))
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#define VICVectCntl20 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x250))
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#define VICVectCntl21 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x254))
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#define VICVectCntl22 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x258))
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#define VICVectCntl23 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x25C))
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#define VICVectCntl24 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x260))
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#define VICVectCntl25 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x264))
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#define VICVectCntl26 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x268))
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#define VICVectCntl27 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x26C))
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#define VICVectCntl28 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x270))
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#define VICVectCntl29 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x274))
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#define VICVectCntl30 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x278))
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#define VICVectCntl31 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x27C))
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#define VICVectAddr (*(volatile unsigned int *)(VIC_BASE_ADDR + 0xF00))
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/* Pin Connect Block */
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#define PINSEL_BASE_ADDR 0xE002C000
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#define PINSEL0 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x00))
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#define PINSEL1 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x04))
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#define PINSEL2 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x08))
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#define PINSEL3 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x0C))
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#define PINSEL4 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x10))
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#define PINSEL5 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x14))
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#define PINSEL6 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x18))
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#define PINSEL7 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x1C))
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#define PINSEL8 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x20))
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#define PINSEL9 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x24))
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#define PINSEL10 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x28))
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#define PINMODE0 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x40))
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#define PINMODE1 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x44))
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#define PINMODE2 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x48))
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#define PINMODE3 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x4C))
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#define PINMODE4 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x50))
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#define PINMODE5 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x54))
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#define PINMODE6 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x58))
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#define PINMODE7 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x5C))
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#define PINMODE8 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x60))
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#define PINMODE9 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x64))
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/* General Purpose Input/Output (GPIO) */
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#define GPIO_BASE_ADDR 0xE0028000
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#define IOPIN0 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x00))
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#define IOSET0 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x04))
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#define IODIR0 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x08))
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#define IOCLR0 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x0C))
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#define IOPIN1 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x10))
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#define IOSET1 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x14))
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#define IODIR1 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x18))
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#define IOCLR1 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x1C))
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/* GPIO Interrupt Registers */
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#define IO0_INT_EN_R (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x90))
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#define IO0_INT_EN_F (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x94))
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#define IO0_INT_STAT_R (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x84))
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#define IO0_INT_STAT_F (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x88))
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#define IO0_INT_CLR (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x8C))
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#define IO2_INT_EN_R (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0xB0))
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#define IO2_INT_EN_F (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0xB4))
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#define IO2_INT_STAT_R (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0xA4))
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#define IO2_INT_STAT_F (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0xA8))
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#define IO2_INT_CLR (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0xAC))
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#define IO_INT_STAT (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x80))
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#define PARTCFG_BASE_ADDR 0x3FFF8000
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#define PARTCFG (*(volatile unsigned int *)(PARTCFG_BASE_ADDR + 0x00))
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/* Fast I/O setup */
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#define FIO_BASE_ADDR 0x3FFFC000
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#define FIO0DIR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x00))
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#define FIO0MASK (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x10))
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#define FIO0PIN (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x14))
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#define FIO0SET (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x18))
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#define FIO0CLR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x1C))
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#define FIO1DIR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x20))
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#define FIO1MASK (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x30))
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#define FIO1PIN (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x34))
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#define FIO1SET (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x38))
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#define FIO1CLR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x3C))
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#define FIO2DIR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x40))
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#define FIO2MASK (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x50))
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#define FIO2PIN (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x54))
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#define FIO2SET (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x58))
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#define FIO2CLR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x5C))
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#define FIO3DIR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x60))
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#define FIO3MASK (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x70))
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#define FIO3PIN (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x74))
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#define FIO3SET (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x78))
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#define FIO3CLR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x7C))
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#define FIO4DIR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x80))
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#define FIO4MASK (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x90))
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#define FIO4PIN (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x94))
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#define FIO4SET (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x98))
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#define FIO4CLR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x9C))
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/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */
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#define FIO0DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01))
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#define FIO1DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21))
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#define FIO2DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x41))
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#define FIO3DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x61))
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#define FIO4DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x81))
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#define FIO0DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02))
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#define FIO1DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22))
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#define FIO2DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x42))
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#define FIO3DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x62))
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#define FIO4DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x82))
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#define FIO0DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03))
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#define FIO1DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23))
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#define FIO2DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x43))
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#define FIO3DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x63))
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#define FIO4DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x83))
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#define FIO0DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x04))
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#define FIO1DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x24))
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#define FIO2DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x44))
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#define FIO3DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x64))
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#define FIO4DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x84))
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#define FIO0DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x00))
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#define FIO1DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x20))
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#define FIO2DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x40))
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#define FIO3DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x60))
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#define FIO4DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x80))
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#define FIO0DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x02))
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#define FIO1DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x22))
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#define FIO2DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x42))
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#define FIO3DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x62))
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#define FIO4DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x82))
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#define FIO0MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10))
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#define FIO1MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30))
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#define FIO2MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x50))
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#define FIO3MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x70))
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#define FIO4MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x90))
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#define FIO0MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11))
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#define FIO1MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21))
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#define FIO2MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x51))
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#define FIO3MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x71))
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#define FIO4MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x91))
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#define FIO0MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12))
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#define FIO1MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32))
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#define FIO2MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x52))
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#define FIO3MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x72))
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#define FIO4MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x92))
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#define FIO0MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13))
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#define FIO1MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33))
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#define FIO2MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x53))
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#define FIO3MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x73))
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#define FIO4MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x93))
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#define FIO0MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x10))
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#define FIO1MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x30))
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#define FIO2MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x50))
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#define FIO3MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x70))
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#define FIO4MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x90))
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#define FIO0MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x12))
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#define FIO1MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x32))
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#define FIO2MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x52))
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#define FIO3MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x72))
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#define FIO4MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x92))
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#define FIO0PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14))
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#define FIO1PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34))
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#define FIO2PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x54))
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#define FIO3PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x74))
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#define FIO4PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x94))
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#define FIO0PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15))
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#define FIO1PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x25))
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#define FIO2PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x55))
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#define FIO3PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x75))
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#define FIO4PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x95))
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#define FIO0PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16))
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#define FIO1PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36))
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#define FIO2PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x56))
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#define FIO3PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x76))
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#define FIO4PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x96))
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#define FIO0PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17))
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#define FIO1PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37))
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#define FIO2PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x57))
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#define FIO3PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x77))
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#define FIO4PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x97))
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#define FIO0PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x14))
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#define FIO1PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x34))
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#define FIO2PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x54))
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#define FIO3PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x74))
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#define FIO4PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x94))
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#define FIO0PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x16))
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#define FIO1PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x36))
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#define FIO2PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x56))
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#define FIO3PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x76))
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#define FIO4PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x96))
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#define FIO0SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18))
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#define FIO1SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38))
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#define FIO2SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x58))
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#define FIO3SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x78))
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#define FIO4SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x98))
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#define FIO0SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19))
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#define FIO1SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x29))
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#define FIO2SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x59))
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#define FIO3SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x79))
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#define FIO4SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x99))
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#define FIO0SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1A))
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#define FIO1SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A))
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#define FIO2SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5A))
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#define FIO3SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7A))
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#define FIO4SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9A))
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#define FIO0SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1B))
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#define FIO1SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B))
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#define FIO2SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5B))
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#define FIO3SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7B))
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#define FIO4SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9B))
326
327
#define FIO0SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x18))
328
#define FIO1SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x38))
329
#define FIO2SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x58))
330
#define FIO3SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x78))
331
#define FIO4SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x98))
332
333
#define FIO0SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1A))
334
#define FIO1SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3A))
335
#define FIO2SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A))
336
#define FIO3SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A))
337
#define FIO4SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A))
338
339
#define FIO0CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C))
340
#define FIO1CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C))
341
#define FIO2CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C))
342
#define FIO3CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C))
343
#define FIO4CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C))
344
345
#define FIO0CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D))
346
#define FIO1CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x2D))
347
#define FIO2CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D))
348
#define FIO3CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D))
349
#define FIO4CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D))
350
351
#define FIO0CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E))
352
#define FIO1CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E))
353
#define FIO2CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E))
354
#define FIO3CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E))
355
#define FIO4CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E))
356
357
#define FIO0CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F))
358
#define FIO1CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F))
359
#define FIO2CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F))
360
#define FIO3CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F))
361
#define FIO4CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F))
362
363
#define FIO0CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C))
364
#define FIO1CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C))
365
#define FIO2CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C))
366
#define FIO3CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C))
367
#define FIO4CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C))
368
369
#define FIO0CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E))
370
#define FIO1CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E))
371
#define FIO2CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E))
372
#define FIO3CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E))
373
#define FIO4CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E))
374
375
376
/* System Control Block(SCB) modules include Memory Accelerator Module,
377
Phase Locked Loop, VPB divider, Power Control, External Interrupt,
378
Reset, and Code Security/Debugging */
379
#define SCB_BASE_ADDR 0xE01FC000
380
381
/* Memory Accelerator Module (MAM) */
382
#define MAMCR (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x000))
383
#define MAMTIM (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x004))
384
#define MEMMAP (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x040))
385
386
/* Phase Locked Loop (PLL) */
387
#define PLLCON (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x080))
388
#define PLLCFG (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x084))
389
#define PLLSTAT (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x088))
390
#define PLLFEED (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x08C))
391
392
/* Power Control */
393
#define PCON (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x0C0))
394
#define PCONP (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x0C4))
395
396
/* Clock Divider */
397
#define APBDIV (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x100))
398
#define CCLKCFG (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x104))
399
#define USBCLKCFG (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x108))
400
#define CLKSRCSEL (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x10C))
401
#define PCLKSEL0 (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x1A8))
402
#define PCLKSEL1 (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x1AC))
403
404
/* External Interrupts */
405
#define EXTINT (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x140))
406
#define INTWAKE (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x144))
407
#define EXTMODE (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x148))
408
#define EXTPOLAR (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x14C))
409
410
/* Reset, reset source identification */
411
#define RSIR (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x180))
412
413
/* RSID, code security protection */
414
#define CSPR (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x184))
415
416
/* AHB configuration */
417
#define AHBCFG1 (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x188))
418
#define AHBCFG2 (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x18C))
419
420
/* System Controls and Status */
421
#define SCS (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x1A0))
422
423
/*MPMC(EMC) registers*/
424
#define STATIC_MEM0_BASE 0x80000000
425
#define STATIC_MEM1_BASE 0x81000000
426
#define STATIC_MEM2_BASE 0x82000000
427
#define STATIC_MEM3_BASE 0x83000000
428
429
#define DYNAMIC_MEM0_BASE 0xA0000000
430
#define DYNAMIC_MEM1_BASE 0xB0000000
431
#define DYNAMIC_MEM2_BASE 0xC0000000
432
#define DYNAMIC_MEM3_BASE 0xD0000000
433
434
/* External Memory Controller (EMC) */
435
#define EMC_BASE_ADDR 0xFFE08000
436
#define EMC_CTRL (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x000))
437
#define EMC_STAT (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x004))
438
#define EMC_CONFIG (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x008))
439
440
/* Dynamic RAM access registers */
441
#define EMC_DYN_CTRL (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x020))
442
#define EMC_DYN_RFSH (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x024))
443
#define EMC_DYN_RD_CFG (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x028))
444
#define EMC_DYN_RP (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x030))
445
#define EMC_DYN_RAS (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x034))
446
#define EMC_DYN_SREX (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x038))
447
#define EMC_DYN_APR (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x03C))
448
#define EMC_DYN_DAL (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x040))
449
#define EMC_DYN_WR (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x044))
450
#define EMC_DYN_RC (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x048))
451
#define EMC_DYN_RFC (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x04C))
452
#define EMC_DYN_XSR (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x050))
453
#define EMC_DYN_RRD (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x054))
454
#define EMC_DYN_MRD (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x058))
455
456
#define EMC_DYN_CFG0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x100))
457
#define EMC_DYN_RASCAS0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x104))
458
#define EMC_DYN_CFG1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x140))
459
#define EMC_DYN_RASCAS1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x144))
460
#define EMC_DYN_CFG2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x160))
461
#define EMC_DYN_RASCAS2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x164))
462
#define EMC_DYN_CFG3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x180))
463
#define EMC_DYN_RASCAS3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x184))
464
465
/* static RAM access registers */
466
#define EMC_STA_CFG0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x200))
467
#define EMC_STA_WAITWEN0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x204))
468
#define EMC_STA_WAITOEN0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x208))
469
#define EMC_STA_WAITRD0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x20C))
470
#define EMC_STA_WAITPAGE0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x210))
471
#define EMC_STA_WAITWR0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x214))
472
#define EMC_STA_WAITTURN0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x218))
473
474
#define EMC_STA_CFG1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x220))
475
#define EMC_STA_WAITWEN1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x224))
476
#define EMC_STA_WAITOEN1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x228))
477
#define EMC_STA_WAITRD1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x22C))
478
#define EMC_STA_WAITPAGE1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x230))
479
#define EMC_STA_WAITWR1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x234))
480
#define EMC_STA_WAITTURN1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x238))
481
482
#define EMC_STA_CFG2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x240))
483
#define EMC_STA_WAITWEN2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x244))
484
#define EMC_STA_WAITOEN2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x248))
485
#define EMC_STA_WAITRD2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x24C))
486
#define EMC_STA_WAITPAGE2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x250))
487
#define EMC_STA_WAITWR2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x254))
488
#define EMC_STA_WAITTURN2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x258))
489
490
#define EMC_STA_CFG3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x260))
491
#define EMC_STA_WAITWEN3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x264))
492
#define EMC_STA_WAITOEN3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x268))
493
#define EMC_STA_WAITRD3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x26C))
494
#define EMC_STA_WAITPAGE3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x270))
495
#define EMC_STA_WAITWR3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x274))
496
#define EMC_STA_WAITTURN3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x278))
497
498
#define EMC_STA_EXT_WAIT (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x880))
499
500
501
/* Timer 0 */
502
#define TMR0_BASE_ADDR 0xE0004000
503
#define T0IR (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x00))
504
#define T0TCR (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x04))
505
#define T0TC (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x08))
506
#define T0PR (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x0C))
507
#define T0PC (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x10))
508
#define T0MCR (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x14))
509
#define T0MR0 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x18))
510
#define T0MR1 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x1C))
511
#define T0MR2 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x20))
512
#define T0MR3 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x24))
513
#define T0CCR (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x28))
514
#define T0CR0 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x2C))
515
#define T0CR1 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x30))
516
#define T0CR2 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x34))
517
#define T0CR3 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x38))
518
#define T0EMR (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x3C))
519
#define T0CTCR (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x70))
520
521
/* Timer 1 */
522
#define TMR1_BASE_ADDR 0xE0008000
523
#define T1IR (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x00))
524
#define T1TCR (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x04))
525
#define T1TC (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x08))
526
#define T1PR (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x0C))
527
#define T1PC (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x10))
528
#define T1MCR (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x14))
529
#define T1MR0 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x18))
530
#define T1MR1 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x1C))
531
#define T1MR2 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x20))
532
#define T1MR3 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x24))
533
#define T1CCR (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x28))
534
#define T1CR0 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x2C))
535
#define T1CR1 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x30))
536
#define T1CR2 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x34))
537
#define T1CR3 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x38))
538
#define T1EMR (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x3C))
539
#define T1CTCR (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x70))
540
541
/* Timer 2 */
542
#define TMR2_BASE_ADDR 0xE0070000
543
#define T2IR (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x00))
544
#define T2TCR (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x04))
545
#define T2TC (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x08))
546
#define T2PR (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x0C))
547
#define T2PC (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x10))
548
#define T2MCR (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x14))
549
#define T2MR0 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x18))
550
#define T2MR1 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x1C))
551
#define T2MR2 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x20))
552
#define T2MR3 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x24))
553
#define T2CCR (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x28))
554
#define T2CR0 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x2C))
555
#define T2CR1 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x30))
556
#define T2CR2 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x34))
557
#define T2CR3 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x38))
558
#define T2EMR (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x3C))
559
#define T2CTCR (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x70))
560
561
/* Timer 3 */
562
#define TMR3_BASE_ADDR 0xE0074000
563
#define T3IR (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x00))
564
#define T3TCR (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x04))
565
#define T3TC (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x08))
566
#define T3PR (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x0C))
567
#define T3PC (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x10))
568
#define T3MCR (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x14))
569
#define T3MR0 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x18))
570
#define T3MR1 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x1C))
571
#define T3MR2 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x20))
572
#define T3MR3 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x24))
573
#define T3CCR (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x28))
574
#define T3CR0 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x2C))
575
#define T3CR1 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x30))
576
#define T3CR2 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x34))
577
#define T3CR3 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x38))
578
#define T3EMR (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x3C))
579
#define T3CTCR (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x70))
580
581
582
/* Pulse Width Modulator (PWM) */
583
#define PWM0_BASE_ADDR 0xE0014000
584
#define PWM0IR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x00))
585
#define PWM0TCR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x04))
586
#define PWM0TC (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x08))
587
#define PWM0PR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x0C))
588
#define PWM0PC (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x10))
589
#define PWM0MCR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x14))
590
#define PWM0MR0 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x18))
591
#define PWM0MR1 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x1C))
592
#define PWM0MR2 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x20))
593
#define PWM0MR3 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x24))
594
#define PWM0CCR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x28))
595
#define PWM0CR0 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x2C))
596
#define PWM0CR1 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x30))
597
#define PWM0CR2 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x34))
598
#define PWM0CR3 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x38))
599
#define PWM0EMR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x3C))
600
#define PWM0MR4 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x40))
601
#define PWM0MR5 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x44))
602
#define PWM0MR6 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x48))
603
#define PWM0PCR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x4C))
604
#define PWM0LER (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x50))
605
#define PWM0CTCR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x70))
606
607
#define PWM1_BASE_ADDR 0xE0018000
608
#define PWM1IR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x00))
609
#define PWM1TCR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x04))
610
#define PWM1TC (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x08))
611
#define PWM1PR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x0C))
612
#define PWM1PC (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x10))
613
#define PWM1MCR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x14))
614
#define PWM1MR0 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x18))
615
#define PWM1MR1 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x1C))
616
#define PWM1MR2 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x20))
617
#define PWM1MR3 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x24))
618
#define PWM1CCR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x28))
619
#define PWM1CR0 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x2C))
620
#define PWM1CR1 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x30))
621
#define PWM1CR2 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x34))
622
#define PWM1CR3 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x38))
623
#define PWM1EMR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x3C))
624
#define PWM1MR4 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x40))
625
#define PWM1MR5 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x44))
626
#define PWM1MR6 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x48))
627
#define PWM1PCR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x4C))
628
#define PWM1LER (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x50))
629
#define PWM1CTCR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x70))
630
631
632
/* Universal Asynchronous Receiver Transmitter 0 (UART0) */
633
#define UART0_BASE_ADDR 0xE000C000
634
#define U0RBR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x00))
635
#define U0THR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x00))
636
#define U0DLL (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x00))
637
#define U0DLM (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x04))
638
#define U0IER (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x04))
639
#define U0IIR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x08))
640
#define U0FCR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x08))
641
#define U0LCR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x0C))
642
#define U0LSR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x14))
643
#define U0SCR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x1C))
644
#define U0ACR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x20))
645
#define U0ICR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x24))
646
#define U0FDR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x28))
647
#define U0TER (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x30))
648
649
/* Universal Asynchronous Receiver Transmitter 1 (UART1) */
650
#define UART1_BASE_ADDR 0xE0010000
651
#define U1RBR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x00))
652
#define U1THR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x00))
653
#define U1DLL (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x00))
654
#define U1DLM (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x04))
655
#define U1IER (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x04))
656
#define U1IIR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x08))
657
#define U1FCR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x08))
658
#define U1LCR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x0C))
659
#define U1MCR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x10))
660
#define U1LSR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x14))
661
#define U1MSR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x18))
662
#define U1SCR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x1C))
663
#define U1ACR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x20))
664
#define U1FDR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x28))
665
#define U1TER (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x30))
666
667
/* Universal Asynchronous Receiver Transmitter 2 (UART2) */
668
#define UART2_BASE_ADDR 0xE0078000
669
#define U2RBR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x00))
670
#define U2THR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x00))
671
#define U2DLL (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x00))
672
#define U2DLM (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x04))
673
#define U2IER (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x04))
674
#define U2IIR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x08))
675
#define U2FCR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x08))
676
#define U2LCR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x0C))
677
#define U2LSR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x14))
678
#define U2SCR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x1C))
679
#define U2ACR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x20))
680
#define U2ICR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x24))
681
#define U2FDR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x28))
682
#define U2TER (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x30))
683
684
/* Universal Asynchronous Receiver Transmitter 3 (UART3) */
685
#define UART3_BASE_ADDR 0xE007C000
686
#define U3RBR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x00))
687
#define U3THR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x00))
688
#define U3DLL (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x00))
689
#define U3DLM (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x04))
690
#define U3IER (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x04))
691
#define U3IIR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x08))
692
#define U3FCR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x08))
693
#define U3LCR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x0C))
694
#define U3LSR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x14))
695
#define U3SCR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x1C))
696
#define U3ACR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x20))
697
#define U3ICR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x24))
698
#define U3FDR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x28))
699
#define U3TER (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x30))
700
701
/* I2C Interface 0 */
702
#define I2C0_BASE_ADDR 0xE001C000
703
#define I20CONSET (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x00))
704
#define I20STAT (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x04))
705
#define I20DAT (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x08))
706
#define I20ADR (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x0C))
707
#define I20SCLH (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x10))
708
#define I20SCLL (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x14))
709
#define I20CONCLR (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x18))
710
//Slightly different naming
711
#define I2C0CONSET (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x00))
712
#define I2C0STAT (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x04))
713
#define I2C0DAT (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x08))
714
#define I2C0ADR (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x0C))
715
#define I2C0SCLH (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x10))
716
#define I2C0SCLL (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x14))
717
#define I2C0CONCLR (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x18))
718
719
720
/* I2C Interface 1 */
721
#define I2C1_BASE_ADDR 0xE005C000
722
#define I21CONSET (*(volatile unsigned int *)(I2C1_BASE_ADDR + 0x00))
723
#define I21STAT (*(volatile unsigned int *)(I2C1_BASE_ADDR + 0x04))
724
#define I21DAT (*(volatile unsigned int *)(I2C1_BASE_ADDR + 0x08))
725
#define I21ADR (*(volatile unsigned int *)(I2C1_BASE_ADDR + 0x0C))
726
#define I21SCLH (*(volatile unsigned int *)(I2C1_BASE_ADDR + 0x10))
727
#define I21SCLL (*(volatile unsigned int *)(I2C1_BASE_ADDR + 0x14))
728
#define I21CONCLR (*(volatile unsigned int *)(I2C1_BASE_ADDR + 0x18))
729
730
/* I2C Interface 2 */
731
#define I2C2_BASE_ADDR 0xE0080000
732
#define I22CONSET (*(volatile unsigned int *)(I2C2_BASE_ADDR + 0x00))
733
#define I22STAT (*(volatile unsigned int *)(I2C2_BASE_ADDR + 0x04))
734
#define I22DAT (*(volatile unsigned int *)(I2C2_BASE_ADDR + 0x08))
735
#define I22ADR (*(volatile unsigned int *)(I2C2_BASE_ADDR + 0x0C))
736
#define I22SCLH (*(volatile unsigned int *)(I2C2_BASE_ADDR + 0x10))
737
#define I22SCLL (*(volatile unsigned int *)(I2C2_BASE_ADDR + 0x14))
738
#define I22CONCLR (*(volatile unsigned int *)(I2C2_BASE_ADDR + 0x18))
739
740
/* SPI0 (Serial Peripheral Interface 0) */
741
#define SPI0_BASE_ADDR 0xE0020000
742
#define S0SPCR (*(volatile unsigned int *)(SPI0_BASE_ADDR + 0x00))
743
#define S0SPSR (*(volatile unsigned int *)(SPI0_BASE_ADDR + 0x04))
744
#define S0SPDR (*(volatile unsigned int *)(SPI0_BASE_ADDR + 0x08))
745
#define S0SPCCR (*(volatile unsigned int *)(SPI0_BASE_ADDR + 0x0C))
746
#define S0SPINT (*(volatile unsigned int *)(SPI0_BASE_ADDR + 0x1C))
747
748
/* SSP0 Controller */
749
#define SSP0_BASE_ADDR 0xE0068000
750
#define SSP0CR0 (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x00))
751
#define SSP0CR1 (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x04))
752
#define SSP0DR (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x08))
753
#define SSP0SR (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x0C))
754
#define SSP0CPSR (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x10))
755
#define SSP0IMSC (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x14))
756
#define SSP0RIS (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x18))
757
#define SSP0MIS (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x1C))
758
#define SSP0ICR (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x20))
759
#define SSP0DMACR (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x24))
760
761
/* SSP1 Controller */
762
#define SSP1_BASE_ADDR 0xE0030000
763
#define SSP1CR0 (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x00))
764
#define SSP1CR1 (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x04))
765
#define SSP1DR (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x08))
766
#define SSP1SR (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x0C))
767
#define SSP1CPSR (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x10))
768
#define SSP1IMSC (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x14))
769
#define SSP1RIS (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x18))
770
#define SSP1MIS (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x1C))
771
#define SSP1ICR (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x20))
772
#define SSP1DMACR (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x24))
773
774
775
/* Real Time Clock */
776
#define RTC_BASE_ADDR 0xE0024000
777
#define RTC_ILR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x00))
778
#define RTC_CTC (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x04))
779
#define RTC_CCR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x08))
780
#define RTC_CIIR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x0C))
781
#define RTC_AMR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x10))
782
#define RTC_CTIME0 (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x14))
783
#define RTC_CTIME1 (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x18))
784
#define RTC_CTIME2 (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x1C))
785
#define RTC_SEC (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x20))
786
#define RTC_MIN (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x24))
787
#define RTC_HOUR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x28))
788
#define RTC_DOM (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x2C))
789
#define RTC_DOW (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x30))
790
#define RTC_DOY (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x34))
791
#define RTC_MONTH (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x38))
792
#define RTC_YEAR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x3C))
793
#define RTC_CISS (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x40))
794
#define RTC_ALSEC (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x60))
795
#define RTC_ALMIN (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x64))
796
#define RTC_ALHOUR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x68))
797
#define RTC_ALDOM (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x6C))
798
#define RTC_ALDOW (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x70))
799
#define RTC_ALDOY (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x74))
800
#define RTC_ALMON (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x78))
801
#define RTC_ALYEAR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x7C))
802
#define RTC_PREINT (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x80))
803
#define RTC_PREFRAC (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x84))
804
805
806
/* A/D Converter 0 (AD0) */
807
#define AD0_BASE_ADDR 0xE0034000
808
#define AD0CR (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x00))
809
#define AD0GDR (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x04))
810
#define AD0INTEN (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x0C))
811
#define AD0DR0 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x10))
812
#define AD0DR1 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x14))
813
#define AD0DR2 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x18))
814
#define AD0DR3 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x1C))
815
#define AD0DR4 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x20))
816
#define AD0DR5 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x24))
817
#define AD0DR6 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x28))
818
#define AD0DR7 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x2C))
819
#define AD0STAT (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x30))
820
821
822
/* D/A Converter */
823
#define DAC_BASE_ADDR 0xE006C000
824
#define DACR (*(volatile unsigned int *)(DAC_BASE_ADDR + 0x00))
825
826
827
/* Watchdog */
828
#define WDG_BASE_ADDR 0xE0000000
829
#define WDMOD (*(volatile unsigned int *)(WDG_BASE_ADDR + 0x00))
830
#define WDTC (*(volatile unsigned int *)(WDG_BASE_ADDR + 0x04))
831
#define WDFEED (*(volatile unsigned int *)(WDG_BASE_ADDR + 0x08))
832
#define WDTV (*(volatile unsigned int *)(WDG_BASE_ADDR + 0x0C))
833
#define WDCLKSEL (*(volatile unsigned int *)(WDG_BASE_ADDR + 0x10))
834
835
/* CAN CONTROLLERS AND ACCEPTANCE FILTER */
836
#define CAN_ACCEPT_BASE_ADDR 0xE003C000
837
#define CAN_AFMR (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x00))
838
#define CAN_SFF_SA (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x04))
839
#define CAN_SFF_GRP_SA (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x08))
840
#define CAN_EFF_SA (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x0C))
841
#define CAN_EFF_GRP_SA (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x10))
842
#define CAN_EOT (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x14))
843
#define CAN_LUT_ERR_ADR (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x18))
844
#define CAN_LUT_ERR (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x1C))
845
846
#define CAN_CENTRAL_BASE_ADDR 0xE0040000
847
#define CAN_TX_SR (*(volatile unsigned int *)(CAN_CENTRAL_BASE_ADDR + 0x00))
848
#define CAN_RX_SR (*(volatile unsigned int *)(CAN_CENTRAL_BASE_ADDR + 0x04))
849
#define CAN_MSR (*(volatile unsigned int *)(CAN_CENTRAL_BASE_ADDR + 0x08))
850
851
#define CAN1_BASE_ADDR 0xE0044000
852
#define CAN1MOD (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x00))
853
#define CAN1CMR (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x04))
854
#define CAN1GSR (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x08))
855
#define CAN1ICR (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x0C))
856
#define CAN1IER (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x10))
857
#define CAN1BTR (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x14))
858
#define CAN1EWL (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x18))
859
#define CAN1SR (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x1C))
860
#define CAN1RFS (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x20))
861
#define CAN1RID (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x24))
862
#define CAN1RDA (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x28))
863
#define CAN1RDB (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x2C))
864
865
#define CAN1TFI1 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x30))
866
#define CAN1TID1 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x34))
867
#define CAN1TDA1 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x38))
868
#define CAN1TDB1 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x3C))
869
#define CAN1TFI2 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x40))
870
#define CAN1TID2 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x44))
871
#define CAN1TDA2 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x48))
872
#define CAN1TDB2 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x4C))
873
#define CAN1TFI3 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x50))
874
#define CAN1TID3 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x54))
875
#define CAN1TDA3 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x58))
876
#define CAN1TDB3 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x5C))
877
878
#define CAN2_BASE_ADDR 0xE0048000
879
#define CAN2MOD (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x00))
880
#define CAN2CMR (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x04))
881
#define CAN2GSR (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x08))
882
#define CAN2ICR (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x0C))
883
#define CAN2IER (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x10))
884
#define CAN2BTR (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x14))
885
#define CAN2EWL (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x18))
886
#define CAN2SR (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x1C))
887
#define CAN2RFS (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x20))
888
#define CAN2RID (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x24))
889
#define CAN2RDA (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x28))
890
#define CAN2RDB (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x2C))
891
892
#define CAN2TFI1 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x30))
893
#define CAN2TID1 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x34))
894
#define CAN2TDA1 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x38))
895
#define CAN2TDB1 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x3C))
896
#define CAN2TFI2 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x40))
897
#define CAN2TID2 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x44))
898
#define CAN2TDA2 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x48))
899
#define CAN2TDB2 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x4C))
900
#define CAN2TFI3 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x50))
901
#define CAN2TID3 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x54))
902
#define CAN2TDA3 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x58))
903
#define CAN2TDB3 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x5C))
904
905
906
/* MultiMedia Card Interface(MCI) Controller */
907
#define MCI_BASE_ADDR 0xE008C000
908
#define MCI_POWER (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x00))
909
#define MCI_CLOCK (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x04))
910
#define MCI_ARGUMENT (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x08))
911
#define MCI_COMMAND (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x0C))
912
#define MCI_RESP_CMD (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x10))
913
#define MCI_RESP0 (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x14))
914
#define MCI_RESP1 (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x18))
915
#define MCI_RESP2 (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x1C))
916
#define MCI_RESP3 (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x20))
917
#define MCI_DATA_TMR (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x24))
918
#define MCI_DATA_LEN (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x28))
919
#define MCI_DATA_CTRL (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x2C))
920
#define MCI_DATA_CNT (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x30))
921
#define MCI_STATUS (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x34))
922
#define MCI_CLEAR (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x38))
923
#define MCI_MASK0 (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x3C))
924
#define MCI_MASK1 (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x40))
925
#define MCI_FIFO_CNT (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x48))
926
#define MCI_FIFO (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x80))
927
928
929
/* I2S Interface Controller (I2S) */
930
#define I2S_BASE_ADDR 0xE0088000
931
#define I2S_DAO (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x00))
932
#define I2S_DAI (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x04))
933
#define I2S_TX_FIFO (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x08))
934
#define I2S_RX_FIFO (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x0C))
935
#define I2S_STATE (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x10))
936
#define I2S_DMA1 (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x14))
937
#define I2S_DMA2 (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x18))
938
#define I2S_IRQ (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x1C))
939
#define I2S_TXRATE (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x20))
940
#define I2S_RXRATE (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x24))
941
942
943
/* General-purpose DMA Controller */
944
#define DMA_BASE_ADDR 0xFFE04000
945
#define GPDMA_INT_STAT (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x000))
946
#define GPDMA_INT_TCSTAT (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x004))
947
#define GPDMA_INT_TCCLR (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x008))
948
#define GPDMA_INT_ERR_STAT (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x00C))
949
#define GPDMA_INT_ERR_CLR (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x010))
950
#define GPDMA_RAW_INT_TCSTAT (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x014))
951
#define GPDMA_RAW_INT_ERR_STAT (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x018))
952
#define GPDMA_ENABLED_CHNS (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x01C))
953
#define GPDMA_SOFT_BREQ (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x020))
954
#define GPDMA_SOFT_SREQ (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x024))
955
#define GPDMA_SOFT_LBREQ (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x028))
956
#define GPDMA_SOFT_LSREQ (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x02C))
957
#define GPDMA_CONFIG (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x030))
958
#define GPDMA_SYNC (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x034))
959
960
/* DMA channel 0 registers */
961
#define GPDMA_CH0_SRC (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x100))
962
#define GPDMA_CH0_DEST (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x104))
963
#define GPDMA_CH0_LLI (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x108))
964
#define GPDMA_CH0_CTRL (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x10C))
965
#define GPDMA_CH0_CFG (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x110))
966
967
/* DMA channel 1 registers */
968
#define GPDMA_CH1_SRC (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x120))
969
#define GPDMA_CH1_DEST (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x124))
970
#define GPDMA_CH1_LLI (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x128))
971
#define GPDMA_CH1_CTRL (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x12C))
972
#define GPDMA_CH1_CFG (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x130))
973
974
975
/* USB Controller */
976
#define USB_INT_BASE_ADDR 0xE01FC1C0
977
#define USB_BASE_ADDR 0xFFE0C200
/* USB Base Address */
978
979
#define USB_INT_STAT (*(volatile unsigned int *)(USB_INT_BASE_ADDR + 0x00))
980
981
/* USB Device Interrupt Registers */
982
#define DEV_INT_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0x00))
983
#define DEV_INT_EN (*(volatile unsigned int *)(USB_BASE_ADDR + 0x04))
984
#define DEV_INT_CLR (*(volatile unsigned int *)(USB_BASE_ADDR + 0x08))
985
#define DEV_INT_SET (*(volatile unsigned int *)(USB_BASE_ADDR + 0x0C))
986
#define DEV_INT_PRIO (*(volatile unsigned int *)(USB_BASE_ADDR + 0x2C))
987
988
/* USB Device Endpoint Interrupt Registers */
989
#define EP_INT_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0x30))
990
#define EP_INT_EN (*(volatile unsigned int *)(USB_BASE_ADDR + 0x34))
991
#define EP_INT_CLR (*(volatile unsigned int *)(USB_BASE_ADDR + 0x38))
992
#define EP_INT_SET (*(volatile unsigned int *)(USB_BASE_ADDR + 0x3C))
993
#define EP_INT_PRIO (*(volatile unsigned int *)(USB_BASE_ADDR + 0x40))
994
995
/* USB Device Endpoint Realization Registers */
996
#define REALIZE_EP (*(volatile unsigned int *)(USB_BASE_ADDR + 0x44))
997
#define EP_INDEX (*(volatile unsigned int *)(USB_BASE_ADDR + 0x48))
998
#define MAXPACKET_SIZE (*(volatile unsigned int *)(USB_BASE_ADDR + 0x4C))
999
1000
/* USB Device Command Reagisters */
1001
#define CMD_CODE (*(volatile unsigned int *)(USB_BASE_ADDR + 0x10))
1002
#define CMD_DATA (*(volatile unsigned int *)(USB_BASE_ADDR + 0x14))
1003
1004
/* USB Device Data Transfer Registers */
1005
#define RX_DATA (*(volatile unsigned int *)(USB_BASE_ADDR + 0x18))
1006
#define TX_DATA (*(volatile unsigned int *)(USB_BASE_ADDR + 0x1C))
1007
#define RX_PLENGTH (*(volatile unsigned int *)(USB_BASE_ADDR + 0x20))
1008
#define TX_PLENGTH (*(volatile unsigned int *)(USB_BASE_ADDR + 0x24))
1009
#define USB_CTRL (*(volatile unsigned int *)(USB_BASE_ADDR + 0x28))
1010
1011
/* USB Device DMA Registers */
1012
#define DMA_REQ_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0x50))
1013
#define DMA_REQ_CLR (*(volatile unsigned int *)(USB_BASE_ADDR + 0x54))
1014
#define DMA_REQ_SET (*(volatile unsigned int *)(USB_BASE_ADDR + 0x58))
1015
#define UDCA_HEAD (*(volatile unsigned int *)(USB_BASE_ADDR + 0x80))
1016
#define EP_DMA_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0x84))
1017
#define EP_DMA_EN (*(volatile unsigned int *)(USB_BASE_ADDR + 0x88))
1018
#define EP_DMA_DIS (*(volatile unsigned int *)(USB_BASE_ADDR + 0x8C))
1019
#define DMA_INT_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0x90))
1020
#define DMA_INT_EN (*(volatile unsigned int *)(USB_BASE_ADDR + 0x94))
1021
#define EOT_INT_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0xA0))
1022
#define EOT_INT_CLR (*(volatile unsigned int *)(USB_BASE_ADDR + 0xA4))
1023
#define EOT_INT_SET (*(volatile unsigned int *)(USB_BASE_ADDR + 0xA8))
1024
#define NDD_REQ_INT_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0xAC))
1025
#define NDD_REQ_INT_CLR (*(volatile unsigned int *)(USB_BASE_ADDR + 0xB0))
1026
#define NDD_REQ_INT_SET (*(volatile unsigned int *)(USB_BASE_ADDR + 0xB4))
1027
#define SYS_ERR_INT_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0xB8))
1028
#define SYS_ERR_INT_CLR (*(volatile unsigned int *)(USB_BASE_ADDR + 0xBC))
1029
#define SYS_ERR_INT_SET (*(volatile unsigned int *)(USB_BASE_ADDR + 0xC0))
1030
1031
1032
/* USB Host Controller */
1033
#define USBHC_BASE_ADDR 0xFFE0C000
1034
#define HC_REVISION (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x00))
1035
#define HC_CONTROL (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x04))
1036
#define HC_CMD_STAT (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x08))
1037
#define HC_INT_STAT (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x0C))
1038
#define HC_INT_EN (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x10))
1039
#define HC_INT_DIS (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x14))
1040
#define HC_HCCA (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x18))
1041
#define HC_PERIOD_CUR_ED (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x1C))
1042
#define HC_CTRL_HEAD_ED (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x20))
1043
#define HC_CTRL_CUR_ED (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x24))
1044
#define HC_BULK_HEAD_ED (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x28))
1045
#define HC_BULK_CUR_ED (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x2C))
1046
#define HC_DONE_HEAD (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x30))
1047
#define HC_FM_INTERVAL (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x34))
1048
#define HC_FM_REMAINING (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x38))
1049
#define HC_FM_NUMBER (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x3C))
1050
#define HC_PERIOD_START (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x40))
1051
#define HC_LS_THRHLD (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x44))
1052
#define HC_RH_DESCA (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x48))
1053
#define HC_RH_DESCB (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x4C))
1054
#define HC_RH_STAT (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x50))
1055
#define HC_RH_PORT_STAT1 (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x54))
1056
#define HC_RH_PORT_STAT2 (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x58))
1057
1058
/* USB OTG Controller */
1059
#define USBOTG_BASE_ADDR 0xFFE0C100
1060
#define OTG_INT_STAT (*(volatile unsigned int *)(USBOTG_BASE_ADDR + 0x00))
1061
#define OTG_INT_EN (*(volatile unsigned int *)(USBOTG_BASE_ADDR + 0x04))
1062
#define OTG_INT_SET (*(volatile unsigned int *)(USBOTG_BASE_ADDR + 0x08))
1063
#define OTG_INT_CLR (*(volatile unsigned int *)(USBOTG_BASE_ADDR + 0x0C))
1064
#define OTG_STAT_CTRL (*(volatile unsigned int *)(USBOTG_BASE_ADDR + 0x10))
1065
#define OTG_TIMER (*(volatile unsigned int *)(USBOTG_BASE_ADDR + 0x14))
1066
1067
#define USBOTG_I2C_BASE_ADDR 0xFFE0C300
1068
#define OTG_I2C_RX (*(volatile unsigned int *)(USBOTG_I2C_BASE_ADDR + 0x00))
1069
#define OTG_I2C_TX (*(volatile unsigned int *)(USBOTG_I2C_BASE_ADDR + 0x00))
1070
#define OTG_I2C_STS (*(volatile unsigned int *)(USBOTG_I2C_BASE_ADDR + 0x04))
1071
#define OTG_I2C_CTL (*(volatile unsigned int *)(USBOTG_I2C_BASE_ADDR + 0x08))
1072
#define OTG_I2C_CLKHI (*(volatile unsigned int *)(USBOTG_I2C_BASE_ADDR + 0x0C))
1073
#define OTG_I2C_CLKLO (*(volatile unsigned int *)(USBOTG_I2C_BASE_ADDR + 0x10))
1074
1075
#define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0
1076
#define OTG_CLK_CTRL (*(volatile unsigned int *)(USBOTG_CLK_BASE_ADDR + 0x04))
1077
#define OTG_CLK_STAT (*(volatile unsigned int *)(USBOTG_CLK_BASE_ADDR + 0x08))
1078
1079
1080
/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */
1081
#define MAC_BASE_ADDR 0xFFE00000
/* AHB Peripheral # 0 */
1082
#define MAC_MAC1 (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x000))
/* MAC config reg 1 */
1083
#define MAC_MAC2 (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x004))
/* MAC config reg 2 */
1084
#define MAC_IPGT (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x008))
/* b2b InterPacketGap reg */
1085
#define MAC_IPGR (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x00C))
/* non b2b InterPacketGap reg */
1086
#define MAC_CLRT (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x010))
/* CoLlision window/ReTry reg */
1087
#define MAC_MAXF (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x014))
/* MAXimum Frame reg */
1088
#define MAC_SUPP (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x018))
/* PHY SUPPort reg */
1089
#define MAC_TEST (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x01C))
/* TEST reg */
1090
#define MAC_MCFG (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x020))
/* MII Mgmt ConFiG reg */
1091
#define MAC_MCMD (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x024))
/* MII Mgmt CoMmanD reg */
1092
#define MAC_MADR (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x028))
/* MII Mgmt ADdRess reg */
1093
#define MAC_MWTD (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x02C))
/* MII Mgmt WriTe Data reg (WO) */
1094
#define MAC_MRDD (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x030))
/* MII Mgmt ReaD Data reg (RO) */
1095
#define MAC_MIND (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x034))
/* MII Mgmt INDicators reg (RO) */
1096
1097
#define MAC_SA0 (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x040))
/* Station Address 0 reg */
1098
#define MAC_SA1 (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x044))
/* Station Address 1 reg */
1099
#define MAC_SA2 (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x048))
/* Station Address 2 reg */
1100
1101
#define MAC_COMMAND (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x100))
/* Command reg */
1102
#define MAC_STATUS (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x104))
/* Status reg (RO) */
1103
#define MAC_RXDESCRIPTOR (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x108))
/* Rx descriptor base address reg */
1104
#define MAC_RXSTATUS (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x10C))
/* Rx status base address reg */
1105
#define MAC_RXDESCRIPTORNUM (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x110))
/* Rx number of descriptors reg */
1106
#define MAC_RXPRODUCEINDEX (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x114))
/* Rx produce index reg (RO) */
1107
#define MAC_RXCONSUMEINDEX (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x118))
/* Rx consume index reg */
1108
#define MAC_TXDESCRIPTOR (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x11C))
/* Tx descriptor base address reg */
1109
#define MAC_TXSTATUS (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x120))
/* Tx status base address reg */
1110
#define MAC_TXDESCRIPTORNUM (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x124))
/* Tx number of descriptors reg */
1111
#define MAC_TXPRODUCEINDEX (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x128))
/* Tx produce index reg */
1112
#define MAC_TXCONSUMEINDEX (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x12C))
/* Tx consume index reg (RO) */
1113
1114
#define MAC_TSV0 (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x158))
/* Tx status vector 0 reg (RO) */
1115
#define MAC_TSV1 (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x15C))
/* Tx status vector 1 reg (RO) */
1116
#define MAC_RSV (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x160))
/* Rx status vector reg (RO) */
1117
1118
#define MAC_FLOWCONTROLCNT (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x170))
/* Flow control counter reg */
1119
#define MAC_FLOWCONTROLSTS (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x174))
/* Flow control status reg */
1120
1121
#define MAC_RXFILTERCTRL (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x200))
/* Rx filter ctrl reg */
1122
#define MAC_RXFILTERWOLSTS (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x204))
/* Rx filter WoL status reg (RO) */
1123
#define MAC_RXFILTERWOLCLR (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x208))
/* Rx filter WoL clear reg (WO) */
1124
1125
#define MAC_HASHFILTERL (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x210))
/* Hash filter LSBs reg */
1126
#define MAC_HASHFILTERH (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x214))
/* Hash filter MSBs reg */
1127
1128
#define MAC_INTSTATUS (*(volatile unsigned int *)(MAC_BASE_ADDR + 0xFE0))
/* Interrupt status reg (RO) */
1129
#define MAC_INTENABLE (*(volatile unsigned int *)(MAC_BASE_ADDR + 0xFE4))
/* Interrupt enable reg */
1130
#define MAC_INTCLEAR (*(volatile unsigned int *)(MAC_BASE_ADDR + 0xFE8))
/* Interrupt clear reg (WO) */
1131
#define MAC_INTSET (*(volatile unsigned int *)(MAC_BASE_ADDR + 0xFEC))
/* Interrupt set reg (WO) */
1132
1133
#define MAC_POWERDOWN (*(volatile unsigned int *)(MAC_BASE_ADDR + 0xFF4))
/* Power-down reg */
1134
#define MAC_MODULEID (*(volatile unsigned int *)(MAC_BASE_ADDR + 0xFFC))
/* Module ID reg (RO) */
1135
1136
1137
#endif
/* __LPC23xx_H */
1138
include
freertos
lpc23xx.h
Generated on Sun Feb 2 2025 21:18:13 for Open Model Railroad Network (OpenMRN) by
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