FemtoLCC

Mechanical

Board outline, mounting hole pattern, drill schedule and design rules.

The board is laid out on an imperial grid, so the inch figures are the round ones. Millimetres follow in brackets.

Board outline

Property
Width3.000 in (76.20 mm)
Height3.750 in (95.25 mm)
Thickness0.063 in (1.6 mm)
Layers4
Copper weight1 oz outer, 1 oz inner

Mounting holes

Four M4 holes on a rectangular pattern, plated, each ringed with eight stitching vias tying the pad through the stackup.

Property
Pattern2.500 × 3.250 in (63.50 × 82.55 mm)
Inset from each edge0.250 in (6.35 mm)
Hole diameter0.169 in (4.3 mm)
Pad diameter0.339 in (8.6 mm)
Stitching via drill0.024 in (0.6 mm)
Stitching vias per hole8

The pattern is centred on the board, so each hole sits a quarter inch in from both nearest edges. H1 is top-left, H2 top-right, H3 bottom-left and H4 bottom-right.

Hole positions from the board’s lower-left corner:

RefXY
H10.250 in (6.35 mm)3.500 in (88.90 mm)
H22.750 in (69.85 mm)3.500 in (88.90 mm)
H30.250 in (6.35 mm)0.250 in (6.35 mm)
H42.750 in (69.85 mm)0.250 in (6.35 mm)

M4 clearance through a 0.169 in hole leaves 0.012 in of play, and the 0.339 in pad is large enough that an M4 washer sits entirely on copper.

Drill schedule

Plated (PTH) — 442 holes

DiameterCountWhat
0.012 in0.30 mm353Signal vias
0.024 in0.60 mm32Mounting hole stitching vias
0.028 in0.70 mm4USB-C P1 shield legs
0.031 in0.80 mm2Solder jumper JP6
0.037 in0.94 mm16RJ45 J2
0.039 in1.00 mm18Pin header J1 (6) and PMOD J4 (12)
0.047 in1.20 mm5Pluggable headers J9, J10
0.051 in1.30 mm8Screw terminals J5J8
0.169 in4.30 mm4M4 mounting holes

Non-plated (NPTH) — 4 holes

DiameterCountWhat
0.023 in0.58 mm1USB-C P1 locating slot, 0.039 × 0.023 in oval
0.026 in0.66 mm1USB-C P1 locating hole
0.130 in3.30 mm2RJ45 J2 mounting posts

Smallest plated drill is 0.012 in (0.30 mm). The smallest non-plated feature is P1’s oval slot — note that 0.023 in is its minor axis, not a round hole, and some fabs quote slots separately.

Design rules

The rules stored in FemtoLCC.kicad_pro are set to JLCPCB’s capability limits:

RuleRule
Clearance0.004 in (0.10 mm)Track width0.004 in (0.10 mm)
Hole to hole0.010 in (0.25 mm)Hole clearance0.008 in (0.20 mm)
Copper to edge0.012 in (0.30 mm)Via diameter0.018 in (0.45 mm)
Annular ring0.005 in (0.13 mm)Text / silk width0.006 in (0.15 mm)

Actual minimums on the board are looser than that floor: 0.008 in (0.20 mm) track and 0.004 in (0.10 mm) space.

track_dangling is set to ignore — the one-ended GND stubs in the driver section are deliberate guard traces, not routing leftovers.

DRC passes with 0 errors and 0 unconnected items, and ERC with 0 violations.